1748 	struct si_power_info *pi = rdev->pm.dpm.priv;  in si_get_pi()
1822 	u32 p_limit1 = rdev->pm.dpm.tdp_limit;  in si_update_dte_from_pl2()
1823 	u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;  in si_update_dte_from_pl2()
2113 	if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)  in si_calculate_adjusted_tdp_limits()
2116 	max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;  in si_calculate_adjusted_tdp_limits()
2119 		*tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;  in si_calculate_adjusted_tdp_limits()
2120 		*near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);  in si_calculate_adjusted_tdp_limits()
2122 		*tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;  in si_calculate_adjusted_tdp_limits()
2123 		adjustment_delta  = rdev->pm.dpm.tdp_limit - *tdp_limit;  in si_calculate_adjusted_tdp_limits()
2124 		if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)  in si_calculate_adjusted_tdp_limits()
2125 			*near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;  in si_calculate_adjusted_tdp_limits()
2147 		struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;  in si_populate_smc_tdp_limits()
2160 						       rdev->pm.dpm.tdp_adjustment,  in si_populate_smc_tdp_limits()
2217 			cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);  in si_populate_smc_tdp_limits_2()
2219 …cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_…  in si_populate_smc_tdp_limits_2()
2379 	if (rdev->pm.dpm.sq_ramping_threshold == 0)  in si_populate_sq_ramping_values()
2401 		if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&  in si_populate_sq_ramping_values()
2520 		&rdev->pm.dpm.dyn_state.cac_leakage_table;  in si_get_cac_std_voltage_max_min()
2657 	si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;  in si_initialize_smc_cac_tables()
2684 	load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;  in si_initialize_smc_cac_tables()
2923 		&rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;  in si_get_vce_clock_voltage()
2986 		if (rdev->pm.dpm.high_pixelclock_count > 1)  in si_apply_state_adjust_rules()
2991 		rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;  in si_apply_state_adjust_rules()
2992 		rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;  in si_apply_state_adjust_rules()
3000 	if ((rdev->pm.dpm.new_active_crtc_count > 1) ||  in si_apply_state_adjust_rules()
3009 	if (rdev->pm.dpm.ac_power)  in si_apply_state_adjust_rules()
3010 		max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in si_apply_state_adjust_rules()
3012 		max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;  in si_apply_state_adjust_rules()
3018 	if (rdev->pm.dpm.ac_power == false) {  in si_apply_state_adjust_rules()
3032 	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,  in si_apply_state_adjust_rules()
3034 	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,  in si_apply_state_adjust_rules()
3036 	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,  in si_apply_state_adjust_rules()
3081 		if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)  in si_apply_state_adjust_rules()
3082 			sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;  in si_apply_state_adjust_rules()
3083 		if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)  in si_apply_state_adjust_rules()
3084 			mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;  in si_apply_state_adjust_rules()
3138 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,  in si_apply_state_adjust_rules()
3141 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,  in si_apply_state_adjust_rules()
3144 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,  in si_apply_state_adjust_rules()
3147 		btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,  in si_apply_state_adjust_rules()
3161 		if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)  in si_apply_state_adjust_rules()
3387 	struct radeon_ps *rps = rdev->pm.dpm.current_ps;  in si_dpm_force_performance_level()
3411 	rdev->pm.dpm.forced_level = level;  in si_dpm_force_performance_level()
3632 	voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;  in si_program_response_times()
3670 	if (rdev->pm.dpm.new_active_crtc_count > 0)  in si_program_display_gap()
3675 	if (rdev->pm.dpm.new_active_crtc_count > 1)  in si_program_display_gap()
3685 	if ((rdev->pm.dpm.new_active_crtc_count > 0) &&  in si_program_display_gap()
3686 	    (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {  in si_program_display_gap()
3689 			if (rdev->pm.dpm.new_active_crtcs & (1 << i))  in si_program_display_gap()
3706 	si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);  in si_program_display_gap()
3959 						&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,  in si_construct_voltage_tables()
3980 						&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,  in si_construct_voltage_tables()
4076 							      &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {  in si_populate_smc_voltage_tables()
4138 	if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {  in si_get_std_voltage_value()
4139 		if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {  in si_get_std_voltage_value()
4140 			if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)  in si_get_std_voltage_value()
4143 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {  in si_get_std_voltage_value()
4145 				    (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {  in si_get_std_voltage_value()
4147 					if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)  in si_get_std_voltage_value()
4149 							rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;  in si_get_std_voltage_value()
4152 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]…  in si_get_std_voltage_value()
4158 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {  in si_get_std_voltage_value()
4160 					    (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {  in si_get_std_voltage_value()
4162 						if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)  in si_get_std_voltage_value()
4164 								rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;  in si_get_std_voltage_value()
4167 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]…  in si_get_std_voltage_value()
4173 			if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)  in si_get_std_voltage_value()
4174 				*std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;  in si_get_std_voltage_value()
4426 						 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,  in si_populate_smc_initial_state()
4512 							 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,  in si_populate_smc_acpi_state()
4539 							 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,  in si_populate_smc_acpi_state()
4680 	struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;  in si_init_smc_table()
4702 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)  in si_init_smc_table()
4705 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {  in si_init_smc_table()
4710 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)  in si_init_smc_table()
4716 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)  in si_init_smc_table()
4719 	if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {  in si_init_smc_table()
4721 		vr_hot_gpio = rdev->pm.dpm.backbias_response_time;  in si_init_smc_table()
4987 	    (rdev->pm.dpm.new_active_crtc_count <= 2)) {  in si_convert_power_level_to_smc()
5052 						       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,  in si_convert_power_level_to_smc()
5142 	for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {  in si_is_state_ulv_compatible()
5144 		    rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {  in si_is_state_ulv_compatible()
5146 			    rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)  in si_is_state_ulv_compatible()
5304 	if (rdev->pm.dpm.new_active_crtc_count == 0)  in si_upload_smc_data()
5308 		if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {  in si_upload_smc_data()
5888 								&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);  in si_patch_dependency_tables_based_on_leakage()
5890 								&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);  in si_patch_dependency_tables_based_on_leakage()
5892 								&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);  in si_patch_dependency_tables_based_on_leakage()
5984 	rdev->pm.dpm.thermal.min_temp = low_temp;  in si_thermal_set_temperature_range()
5985 	rdev->pm.dpm.thermal.max_temp = high_temp;  in si_thermal_set_temperature_range()
6024 		rdev->pm.dpm.fan.ucode_fan_control = false;  in si_thermal_setup_fan_table()
6031 		rdev->pm.dpm.fan.ucode_fan_control = false;  in si_thermal_setup_fan_table()
6035 	tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;  in si_thermal_setup_fan_table()
6039 	t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;  in si_thermal_setup_fan_table()
6040 	t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;  in si_thermal_setup_fan_table()
6042 	pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;  in si_thermal_setup_fan_table()
6043 	pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;  in si_thermal_setup_fan_table()
6048 	fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);  in si_thermal_setup_fan_table()
6049 	fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);  in si_thermal_setup_fan_table()
6050 	fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);  in si_thermal_setup_fan_table()
6057 	fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);  in si_thermal_setup_fan_table()
6067 	fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *  in si_thermal_setup_fan_table()
6083 		rdev->pm.dpm.fan.ucode_fan_control = false;  in si_thermal_setup_fan_table()
6180 		if (rdev->pm.dpm.fan.ucode_fan_control)  in si_fan_ctrl_set_mode()
6185 		if (rdev->pm.dpm.fan.ucode_fan_control)  in si_fan_ctrl_set_mode()
6242 	if (rdev->pm.dpm.fan.ucode_fan_control)
6275 	if (rdev->pm.dpm.fan.ucode_fan_control) {  in si_thermal_start_smc_fan_control()
6307 	if (rdev->pm.dpm.fan.ucode_fan_control) {  in si_thermal_start_thermal_controller()
6336 	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;  in si_dpm_enable()
6481 	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;  in si_dpm_disable()
6505 	struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;  in si_dpm_pre_set_power_state()
6517 	struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;  in si_power_control_set_level()
6709 		rdev->pm.dpm.boot_ps = rps;  in si_parse_pplib_non_clock_info()
6711 		rdev->pm.dpm.uvd_ps = rps;  in si_parse_pplib_non_clock_info()
6783 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;  in si_parse_pplib_clock_info()
6784 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;  in si_parse_pplib_clock_info()
6785 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;  in si_parse_pplib_clock_info()
6786 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;  in si_parse_pplib_clock_info()
6822 	rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,  in si_parse_power_table()
6825 	if (!rdev->pm.dpm.ps)  in si_parse_power_table()
6838 			kfree(rdev->pm.dpm.ps);  in si_parse_power_table()
6841 		rdev->pm.dpm.ps[i].ps_priv = ps;  in si_parse_power_table()
6842 		si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],  in si_parse_power_table()
6857 						  &rdev->pm.dpm.ps[i], k,  in si_parse_power_table()
6863 	rdev->pm.dpm.num_ps = state_array->ucNumEntries;  in si_parse_power_table()
6868 		clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;  in si_parse_power_table()
6875 		rdev->pm.dpm.vce_states[i].sclk = sclk;  in si_parse_power_table()
6876 		rdev->pm.dpm.vce_states[i].mclk = mclk;  in si_parse_power_table()
6896 	rdev->pm.dpm.priv = si_pi;  in si_dpm_init()
6942 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =  in si_dpm_init()
6946 	if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {  in si_dpm_init()
6950 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;  in si_dpm_init()
6951 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;  in si_dpm_init()
6952 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;  in si_dpm_init()
6953 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;  in si_dpm_init()
6954 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;  in si_dpm_init()
6955 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;  in si_dpm_init()
6956 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;  in si_dpm_init()
6957 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;  in si_dpm_init()
6958 	rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;  in si_dpm_init()
6960 	if (rdev->pm.dpm.voltage_response_time == 0)  in si_dpm_init()
6961 		rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;  in si_dpm_init()
6962 	if (rdev->pm.dpm.backbias_response_time == 0)  in si_dpm_init()
6963 		rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;  in si_dpm_init()
7040 	rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;  in si_dpm_init()
7041 	rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;  in si_dpm_init()
7042 	rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;  in si_dpm_init()
7043 	rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;  in si_dpm_init()
7044 	rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;  in si_dpm_init()
7045 	rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;  in si_dpm_init()
7046 	rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;  in si_dpm_init()
7051 	if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||  in si_dpm_init()
7052 	    (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))  in si_dpm_init()
7053 		rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =  in si_dpm_init()
7054 			rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in si_dpm_init()
7065 	for (i = 0; i < rdev->pm.dpm.num_ps; i++) {  in si_dpm_fini()
7066 		kfree(rdev->pm.dpm.ps[i].ps_priv);  in si_dpm_fini()
7068 	kfree(rdev->pm.dpm.ps);  in si_dpm_fini()
7069 	kfree(rdev->pm.dpm.priv);  in si_dpm_fini()
7070 	kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);  in si_dpm_fini()