Lines Matching refs:rlc
5221 static void si_update_rlc(struct radeon_device *rdev, u32 rlc) in si_update_rlc() argument
5226 if (tmp != rlc) in si_update_rlc()
5227 WREG32(RLC_CNTL, rlc); in si_update_rlc()
5283 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_gfx_cgpg()
5289 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5689 if (rdev->rlc.cs_data == NULL) in si_get_csb_size()
5697 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_size()
5721 if (rdev->rlc.cs_data == NULL) in si_get_csb_buffer()
5733 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_buffer()
5785 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5786 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5791 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5792 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
6644 rdev->rlc.reg_list = verde_rlc_save_restore_register_list; in si_startup()
6645 rdev->rlc.reg_list_size = in si_startup()
6648 rdev->rlc.cs_data = si_cs_data; in si_startup()