48 static const u32 crtc_offsets[2] =  variable
310 		crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;  in rv515_mc_stop()
313 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);  in rv515_mc_stop()
316 				WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);  in rv515_mc_stop()
318 				WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);  in rv515_mc_stop()
319 				WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);  in rv515_mc_stop()
330 			WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);  in rv515_mc_stop()
331 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);  in rv515_mc_stop()
333 			WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);  in rv515_mc_stop()
334 			WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);  in rv515_mc_stop()
366 			tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);  in rv515_mc_stop()
369 				WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);  in rv515_mc_stop()
371 			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);  in rv515_mc_stop()
374 				WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);  in rv515_mc_stop()
400 		WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],  in rv515_mc_resume()
402 		WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],  in rv515_mc_resume()
410 			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);  in rv515_mc_resume()
414 				WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);  in rv515_mc_resume()
416 			tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);  in rv515_mc_resume()
419 				WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);  in rv515_mc_resume()
421 			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);  in rv515_mc_resume()
424 				WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);  in rv515_mc_resume()
427 				tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);  in rv515_mc_resume()
452 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);  in rv515_mc_resume()
454 			WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);  in rv515_mc_resume()