Lines Matching refs:RREG32
158 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; in rs400_gart_enable()
162 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; in rs400_gart_enable()
249 tmp = RREG32(RADEON_MC_STATUS); in rs400_mc_wait_for_idle()
264 RREG32(RADEON_MC_STATUS)); in rs400_gpu_init()
278 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; in rs400_mc_init()
292 r = RREG32(RS480_NB_MC_DATA); in rs400_mc_rreg()
317 tmp = RREG32(RADEON_HOST_PATH_CNTL); in rs400_debugfs_gart_info()
319 tmp = RREG32(RADEON_BUS_CNTL); in rs400_debugfs_gart_info()
332 tmp = RREG32(RS690_HDP_FB_LOCATION); in rs400_debugfs_gart_info()
335 tmp = RREG32(RADEON_AGP_BASE); in rs400_debugfs_gart_info()
337 tmp = RREG32(RS480_AGP_BASE_2); in rs400_debugfs_gart_info()
339 tmp = RREG32(RADEON_MC_AGP_LOCATION); in rs400_debugfs_gart_info()
447 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in rs400_startup()
477 RREG32(R_000E40_RBBM_STATUS), in rs400_resume()
478 RREG32(R_0007C0_CP_STAT)); in rs400_resume()
551 RREG32(R_000E40_RBBM_STATUS), in rs400_init()
552 RREG32(R_0007C0_CP_STAT)); in rs400_init()