751 		p1pll->pll_out_min = RBIOS32(pll_info + 0x12);  in radeon_combios_get_clock_info()
752 		p1pll->pll_out_max = RBIOS32(pll_info + 0x16);  in radeon_combios_get_clock_info()
757 			p1pll->pll_in_min = RBIOS32(pll_info + 0x36);  in radeon_combios_get_clock_info()
758 			p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);  in radeon_combios_get_clock_info()
768 		spll->pll_out_min = RBIOS32(pll_info + 0x1e);  in radeon_combios_get_clock_info()
769 		spll->pll_out_max = RBIOS32(pll_info + 0x22);  in radeon_combios_get_clock_info()
772 			spll->pll_in_min = RBIOS32(pll_info + 0x48);  in radeon_combios_get_clock_info()
773 			spll->pll_in_max = RBIOS32(pll_info + 0x4c);  in radeon_combios_get_clock_info()
783 		mpll->pll_out_min = RBIOS32(pll_info + 0x2a);  in radeon_combios_get_clock_info()
784 		mpll->pll_out_max = RBIOS32(pll_info + 0x2e);  in radeon_combios_get_clock_info()
787 			mpll->pll_in_min = RBIOS32(pll_info + 0x5a);  in radeon_combios_get_clock_info()
788 			mpll->pll_in_max = RBIOS32(pll_info + 0x5e);  in radeon_combios_get_clock_info()
806 		if (RBIOS32(pll_info + 0x16))  in radeon_combios_get_clock_info()
807 			rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);  in radeon_combios_get_clock_info()
1218 		panel_setup = RBIOS32(lcd_info + 0x39);  in radeon_combios_get_lvds_info()
1354 				    RBIOS32(tmds_info + i * 10 + 0x08);  in radeon_legacy_get_tmds_info_from_combios()
1368 				    RBIOS32(tmds_info + stride + 0x08);  in radeon_legacy_get_tmds_info_from_combios()
2569 								      RBIOS32(lcd_ddc_info + 3),  in radeon_get_legacy_connector_info_from_bios()
2570 								      RBIOS32(lcd_ddc_info + 7));  in radeon_get_legacy_connector_info_from_bios()
2577 								      RBIOS32(lcd_ddc_info + 3),  in radeon_get_legacy_connector_info_from_bios()
2578 								      RBIOS32(lcd_ddc_info + 7));  in radeon_get_legacy_connector_info_from_bios()
2737 			rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);  in radeon_combios_get_power_modes()
2738 			rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);  in radeon_combios_get_power_modes()
2912 						val = RBIOS32(index);  in radeon_combios_external_tmds_setup()
2918 						and_mask = RBIOS32(index);  in radeon_combios_external_tmds_setup()
2920 						or_mask = RBIOS32(index);  in radeon_combios_external_tmds_setup()
2967 					val = RBIOS32(index);  in radeon_combios_external_tmds_setup()
2972 					and_mask = RBIOS32(index);  in radeon_combios_external_tmds_setup()
2974 					or_mask = RBIOS32(index);  in radeon_combios_external_tmds_setup()
2987 					and_mask = RBIOS32(index);  in radeon_combios_external_tmds_setup()
2989 					or_mask = RBIOS32(index);  in radeon_combios_external_tmds_setup()
3029 				val = RBIOS32(offset);  in combios_parse_mmio_table()
3034 				val = RBIOS32(offset);  in combios_parse_mmio_table()
3039 				and_mask = RBIOS32(offset);  in combios_parse_mmio_table()
3041 				or_mask = RBIOS32(offset);  in combios_parse_mmio_table()
3049 				and_mask = RBIOS32(offset);  in combios_parse_mmio_table()
3051 				or_mask = RBIOS32(offset);  in combios_parse_mmio_table()
3108 				val = RBIOS32(offset);  in combios_parse_pll_table()
3280 			mem_cntl = RBIOS32(offset + 1);  in combios_write_ram_size()