Lines Matching refs:ib
357 volatile u32 *ib = p->ib.ptr; in r600_cs_track_validate_cb() local
467 ib[track->cb_color_size_idx[i]] = tmp; in r600_cs_track_validate_cb()
526 volatile u32 *ib = p->ib.ptr; in r600_cs_track_validate_db() local
564 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); in r600_cs_track_validate_db()
833 volatile uint32_t *ib; in r600_cs_common_vline_parse() local
835 ib = p->ib.ptr; in r600_cs_common_vline_parse()
898 ib[h_idx + 2] = PACKET2(0); in r600_cs_common_vline_parse()
899 ib[h_idx + 3] = PACKET2(0); in r600_cs_common_vline_parse()
900 ib[h_idx + 4] = PACKET2(0); in r600_cs_common_vline_parse()
901 ib[h_idx + 5] = PACKET2(0); in r600_cs_common_vline_parse()
902 ib[h_idx + 6] = PACKET2(0); in r600_cs_common_vline_parse()
903 ib[h_idx + 7] = PACKET2(0); in r600_cs_common_vline_parse()
904 ib[h_idx + 8] = PACKET2(0); in r600_cs_common_vline_parse()
908 ib[h_idx] = header; in r600_cs_common_vline_parse()
909 ib[h_idx + 4] = vline_status[crtc_id] >> 2; in r600_cs_common_vline_parse()
971 u32 m, i, tmp, *ib; in r600_cs_check_reg() local
982 ib = p->ib.ptr; in r600_cs_check_reg()
1021 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1040 ib[idx] &= C_028010_ARRAY_MODE; in r600_cs_check_reg()
1043 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); in r600_cs_check_reg()
1046 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); in r600_cs_check_reg()
1083 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1104 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1142 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); in r600_cs_check_reg()
1145 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); in r600_cs_check_reg()
1204 ib[idx] = track->cb_color_base_last[tmp]; in r600_cs_check_reg()
1212 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8; in r600_cs_check_reg()
1213 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1235 ib[idx] = track->cb_color_base_last[tmp]; in r600_cs_check_reg()
1243 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8; in r600_cs_check_reg()
1244 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1280 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1281 track->cb_color_base_last[tmp] = ib[idx]; in r600_cs_check_reg()
1294 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1307 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1314 ib[idx] |= 3; in r600_cs_check_reg()
1376 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1385 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1629 volatile u32 *ib; in r600_packet3_check() local
1637 ib = p->ib.ptr; in r600_packet3_check()
1675 ib[idx + 0] = offset; in r600_packet3_check()
1676 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); in r600_packet3_check()
1716 ib[idx+0] = offset; in r600_packet3_check()
1717 ib[idx+1] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1768 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0); in r600_packet3_check()
1769 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1812 ib[idx] = offset; in r600_packet3_check()
1813 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in r600_packet3_check()
1842 ib[idx+2] = offset; in r600_packet3_check()
1843 ib[idx+3] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1860 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
1880 ib[idx+1] = offset & 0xfffffff8; in r600_packet3_check()
1881 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1902 ib[idx+1] = offset & 0xfffffffc; in r600_packet3_check()
1903 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in r600_packet3_check()
1966 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); in r600_packet3_check()
1968 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); in r600_packet3_check()
1986 ib[idx+1+(i*7)+2] += base_offset; in r600_packet3_check()
1987 ib[idx+1+(i*7)+3] += mip_offset; in r600_packet3_check()
2004 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset; in r600_packet3_check()
2008 ib[idx+1+(i*8)+0] = offset64; in r600_packet3_check()
2009 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | in r600_packet3_check()
2117 ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
2151 ib[idx+1] = offset; in r600_packet3_check()
2152 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2170 ib[idx+3] = offset; in r600_packet3_check()
2171 ib[idx+4] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2199 ib[idx+0] = offset; in r600_packet3_check()
2200 ib[idx+1] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2224 ib[idx+1] = offset; in r600_packet3_check()
2225 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2248 ib[idx+3] = offset; in r600_packet3_check()
2249 ib[idx+4] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2319 for (r = 0; r < p->ib.length_dw; r++) { in r600_cs_parse()
2320 pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]); in r600_cs_parse()
2379 volatile u32 *ib = p->ib.ptr; in r600_dma_cs_parse() local
2407 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2413 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2414 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2441 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2445 ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2446 ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2451 ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2452 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2456 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2466 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2467 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2468 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2469 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2477 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2478 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2479 ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2480 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16; in r600_dma_cs_parse()
2512 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2513 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; in r600_dma_cs_parse()
2525 for (r = 0; r < p->ib->length_dw; r++) { in r600_dma_cs_parse()
2526 pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]); in r600_dma_cs_parse()