641 	u32 idx_value;  in r300_packet0_check()  local
645 	idx_value = radeon_get_ib_value(p, idx);  in r300_packet0_check()
677 		track->cb[i].offset = idx_value;  in r300_packet0_check()
679 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
690 		track->zb.offset = idx_value;  in r300_packet0_check()
692 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
720 			ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */  in r300_packet0_check()
721 				  ((idx_value & ~31) + (u32)reloc->gpu_offset);  in r300_packet0_check()
730 			tmp = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
740 		track->vap_vf_cntl = idx_value;  in r300_packet0_check()
744 		track->vtx_size = idx_value & 0x7F;  in r300_packet0_check()
748 		track->max_indx = idx_value & 0x00FFFFFFUL;  in r300_packet0_check()
754 		track->vap_alt_nverts = idx_value & 0xFFFFFF;  in r300_packet0_check()
758 		track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;  in r300_packet0_check()
767 		if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */  in r300_packet0_check()
772 		track->num_cb = ((idx_value >> 5) & 0x3) + 1;  in r300_packet0_check()
799 			tmp = idx_value & ~(0x7 << 16);  in r300_packet0_check()
804 		track->cb[i].pitch = idx_value & 0x3FFE;  in r300_packet0_check()
805 		switch (((idx_value >> 21) & 0xF)) {  in r300_packet0_check()
820 					  ((idx_value >> 21) & 0xF));  in r300_packet0_check()
835 				  ((idx_value >> 21) & 0xF));  in r300_packet0_check()
842 		if (idx_value & 2) {  in r300_packet0_check()
851 		switch ((idx_value & 0xF)) {  in r300_packet0_check()
861 				  (idx_value & 0xF));  in r300_packet0_check()
884 			tmp = idx_value & ~(0x7 << 16);  in r300_packet0_check()
888 		track->zb.pitch = idx_value & 0x3FFC;  in r300_packet0_check()
896 			enabled = !!(idx_value & (1 << i));  in r300_packet0_check()
919 		tmp = (idx_value >> 25) & 0x3;  in r300_packet0_check()
921 		switch ((idx_value & 0x1F)) {  in r300_packet0_check()
970 					  (idx_value & 0x1F));  in r300_packet0_check()
982 				  (idx_value & 0x1F));  in r300_packet0_check()
1005 		tmp = idx_value & 0x7;  in r300_packet0_check()
1009 		tmp = (idx_value >> 3) & 0x7;  in r300_packet0_check()
1033 		tmp = idx_value & 0x3FFF;  in r300_packet0_check()
1036 			tmp = ((idx_value >> 15) & 1) << 11;  in r300_packet0_check()
1038 			tmp = ((idx_value >> 16) & 1) << 11;  in r300_packet0_check()
1042 			if (idx_value & (1 << 14)) {  in r300_packet0_check()
1047 		} else if (idx_value & (1 << 14)) {  in r300_packet0_check()
1071 		tmp = idx_value & 0x7FF;  in r300_packet0_check()
1073 		tmp = (idx_value >> 11) & 0x7FF;  in r300_packet0_check()
1075 		tmp = (idx_value >> 26) & 0xF;  in r300_packet0_check()
1077 		tmp = idx_value & (1 << 31);  in r300_packet0_check()
1079 		tmp = (idx_value >> 22) & 0xF;  in r300_packet0_check()
1091 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1095 		track->color_channel_mask = idx_value;  in r300_packet0_check()
1103 			if (idx_value & 0x1)  in r300_packet0_check()
1104 				ib[idx] = idx_value & ~1;  in r300_packet0_check()
1109 		track->zb_cb_clear = !!(idx_value & (1 << 5));  in r300_packet0_check()
1113 			if (idx_value & (R300_HIZ_ENABLE |  in r300_packet0_check()
1122 		track->blend_read_enable = !!(idx_value & (1 << 2));  in r300_packet0_check()
1134 		track->aa.offset = idx_value;  in r300_packet0_check()
1136 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1139 		track->aa.pitch = idx_value & 0x3FFE;  in r300_packet0_check()
1143 		track->aaresolve = idx_value & 0x1;  in r300_packet0_check()
1150 		if (idx_value && (p->rdev->hyperz_filp != p->filp))  in r300_packet0_check()
1154 		if (idx_value && (p->rdev->hyperz_filp != p->filp))  in r300_packet0_check()
1172 	       reg, idx, idx_value);  in r300_packet0_check()