Lines Matching refs:WREG32
51 WREG32(TN_SMC_IND_INDEX_0, (reg)); in tn_smc_rreg()
62 WREG32(TN_SMC_IND_INDEX_0, (reg)); in tn_smc_wreg()
63 WREG32(TN_SMC_IND_DATA_0, (v)); in tn_smc_wreg()
677 WREG32(MC_SHARED_BLACKOUT_CNTL, 1); in ni_mc_load_microcode()
681 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ni_mc_load_microcode()
682 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in ni_mc_load_microcode()
686 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); in ni_mc_load_microcode()
687 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); in ni_mc_load_microcode()
692 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); in ni_mc_load_microcode()
695 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ni_mc_load_microcode()
696 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); in ni_mc_load_microcode()
697 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); in ni_mc_load_microcode()
707 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); in ni_mc_load_microcode()
1006 WREG32((0x2c14 + j), 0x00000000); in cayman_gpu_init()
1007 WREG32((0x2c18 + j), 0x00000000); in cayman_gpu_init()
1008 WREG32((0x2c1c + j), 0x00000000); in cayman_gpu_init()
1009 WREG32((0x2c20 + j), 0x00000000); in cayman_gpu_init()
1010 WREG32((0x2c24 + j), 0x00000000); in cayman_gpu_init()
1013 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in cayman_gpu_init()
1014 WREG32(SRBM_INT_CNTL, 0x1); in cayman_gpu_init()
1015 WREG32(SRBM_INT_ACK, 0x1); in cayman_gpu_init()
1095 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init()
1096 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init()
1115 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init()
1116 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init()
1124 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in cayman_gpu_init()
1125 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in cayman_gpu_init()
1127 WREG32(GB_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
1128 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
1130 WREG32(DMIF_ADDR_CALC, gb_addr_config); in cayman_gpu_init()
1131 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
1132 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in cayman_gpu_init()
1133 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in cayman_gpu_init()
1134 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
1135 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
1136 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in cayman_gpu_init()
1155 WREG32(GB_BACKEND_MAP, tmp); in cayman_gpu_init()
1160 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable); in cayman_gpu_init()
1161 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable); in cayman_gpu_init()
1162 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable); in cayman_gpu_init()
1163 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable); in cayman_gpu_init()
1168 WREG32(CGTS_SM_CTRL_REG, OVERRIDE); in cayman_gpu_init()
1169 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg); in cayman_gpu_init()
1172 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); in cayman_gpu_init()
1176 WREG32(SX_DEBUG_1, sx_debug_1); in cayman_gpu_init()
1181 WREG32(SMX_DC_CTL0, smx_dc_ctl0); in cayman_gpu_init()
1183 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE); in cayman_gpu_init()
1186 WREG32(VGT_OFFCHIP_LDS_BASE, 0); in cayman_gpu_init()
1187 WREG32(SQ_LSTMP_RING_BASE, 0); in cayman_gpu_init()
1188 WREG32(SQ_HSTMP_RING_BASE, 0); in cayman_gpu_init()
1189 WREG32(SQ_ESTMP_RING_BASE, 0); in cayman_gpu_init()
1190 WREG32(SQ_GSTMP_RING_BASE, 0); in cayman_gpu_init()
1191 WREG32(SQ_VSTMP_RING_BASE, 0); in cayman_gpu_init()
1192 WREG32(SQ_PSTMP_RING_BASE, 0); in cayman_gpu_init()
1194 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO); in cayman_gpu_init()
1196 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1… in cayman_gpu_init()
1200 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) | in cayman_gpu_init()
1205 WREG32(VGT_NUM_INSTANCES, 1); in cayman_gpu_init()
1207 WREG32(CP_PERFMON_CNTL, 0); in cayman_gpu_init()
1209 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) | in cayman_gpu_init()
1214 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4)); in cayman_gpu_init()
1215 WREG32(SQ_CONFIG, (VC_ENABLE | in cayman_gpu_init()
1220 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE); in cayman_gpu_init()
1222 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | in cayman_gpu_init()
1225 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | in cayman_gpu_init()
1228 WREG32(VGT_GS_VERTEX_REUSE, 16); in cayman_gpu_init()
1229 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in cayman_gpu_init()
1231 WREG32(CB_PERF_CTR0_SEL_0, 0); in cayman_gpu_init()
1232 WREG32(CB_PERF_CTR0_SEL_1, 0); in cayman_gpu_init()
1233 WREG32(CB_PERF_CTR1_SEL_0, 0); in cayman_gpu_init()
1234 WREG32(CB_PERF_CTR1_SEL_1, 0); in cayman_gpu_init()
1235 WREG32(CB_PERF_CTR2_SEL_0, 0); in cayman_gpu_init()
1236 WREG32(CB_PERF_CTR2_SEL_1, 0); in cayman_gpu_init()
1237 WREG32(CB_PERF_CTR3_SEL_0, 0); in cayman_gpu_init()
1238 WREG32(CB_PERF_CTR3_SEL_1, 0); in cayman_gpu_init()
1242 WREG32(HDP_MISC_CNTL, tmp); in cayman_gpu_init()
1245 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); in cayman_gpu_init()
1247 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); in cayman_gpu_init()
1268 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); in cayman_pcie_gart_tlb_flush()
1271 WREG32(VM_INVALIDATE_REQUEST, 1); in cayman_pcie_gart_tlb_flush()
1286 WREG32(MC_VM_MX_L1_TLB_CNTL, in cayman_pcie_gart_enable()
1294 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in cayman_pcie_gart_enable()
1300 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cayman_pcie_gart_enable()
1301 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cayman_pcie_gart_enable()
1305 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in cayman_pcie_gart_enable()
1306 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in cayman_pcie_gart_enable()
1307 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in cayman_pcie_gart_enable()
1308 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in cayman_pcie_gart_enable()
1310 WREG32(VM_CONTEXT0_CNTL2, 0); in cayman_pcie_gart_enable()
1311 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cayman_pcie_gart_enable()
1314 WREG32(0x15D4, 0); in cayman_pcie_gart_enable()
1315 WREG32(0x15D8, 0); in cayman_pcie_gart_enable()
1316 WREG32(0x15DC, 0); in cayman_pcie_gart_enable()
1324 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0); in cayman_pcie_gart_enable()
1325 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), in cayman_pcie_gart_enable()
1327 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), in cayman_pcie_gart_enable()
1332 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, in cayman_pcie_gart_enable()
1334 WREG32(VM_CONTEXT1_CNTL2, 4); in cayman_pcie_gart_enable()
1335 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cayman_pcie_gart_enable()
1368 WREG32(VM_CONTEXT0_CNTL, 0); in cayman_pcie_gart_disable()
1369 WREG32(VM_CONTEXT1_CNTL, 0); in cayman_pcie_gart_disable()
1371 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING | in cayman_pcie_gart_disable()
1375 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_disable()
1379 WREG32(VM_L2_CNTL2, 0); in cayman_pcie_gart_disable()
1380 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cayman_pcie_gart_disable()
1395 WREG32(SRBM_GFX_CNTL, RINGID(ring)); in cayman_cp_int_cntl_setup()
1396 WREG32(CP_INT_CNTL, cp_int_cntl); in cayman_cp_int_cntl_setup()
1464 WREG32(CP_ME_CNTL, 0); in cayman_cp_enable()
1468 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in cayman_cp_enable()
1469 WREG32(SCRATCH_UMSK, 0); in cayman_cp_enable()
1512 WREG32(CP_RB0_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1515 WREG32(CP_RB1_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1518 WREG32(CP_RB2_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1534 WREG32(CP_PFP_UCODE_ADDR, 0); in cayman_cp_load_microcode()
1536 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); in cayman_cp_load_microcode()
1537 WREG32(CP_PFP_UCODE_ADDR, 0); in cayman_cp_load_microcode()
1540 WREG32(CP_ME_RAM_WADDR, 0); in cayman_cp_load_microcode()
1542 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); in cayman_cp_load_microcode()
1544 WREG32(CP_PFP_UCODE_ADDR, 0); in cayman_cp_load_microcode()
1545 WREG32(CP_ME_RAM_WADDR, 0); in cayman_cp_load_microcode()
1546 WREG32(CP_ME_RAM_RADDR, 0); in cayman_cp_load_microcode()
1665 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | in cayman_cp_resume()
1673 WREG32(GRBM_SOFT_RESET, 0); in cayman_cp_resume()
1676 WREG32(CP_SEM_WAIT_TIMER, 0x0); in cayman_cp_resume()
1677 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in cayman_cp_resume()
1680 WREG32(CP_RB_WPTR_DELAY, 0); in cayman_cp_resume()
1682 WREG32(CP_DEBUG, (1 << 27)); in cayman_cp_resume()
1685 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in cayman_cp_resume()
1686 WREG32(SCRATCH_UMSK, 0xff); in cayman_cp_resume()
1699 WREG32(cp_rb_cntl[i], rb_cntl); in cayman_cp_resume()
1703 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC); in cayman_cp_resume()
1704 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF); in cayman_cp_resume()
1710 WREG32(cp_rb_base[i], ring->gpu_addr >> 8); in cayman_cp_resume()
1719 WREG32(cp_rb_rptr[i], 0); in cayman_cp_resume()
1720 WREG32(cp_rb_wptr[i], ring->wptr); in cayman_cp_resume()
1846 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in cayman_gpu_soft_reset()
1852 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
1859 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
1923 WREG32(GRBM_SOFT_RESET, tmp); in cayman_gpu_soft_reset()
1929 WREG32(GRBM_SOFT_RESET, tmp); in cayman_gpu_soft_reset()
1937 WREG32(SRBM_SOFT_RESET, tmp); in cayman_gpu_soft_reset()
1943 WREG32(SRBM_SOFT_RESET, tmp); in cayman_gpu_soft_reset()