1300 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);  in dce4_program_fmt()  local
1348 	WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);  in dce4_program_fmt()
1421 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in evergreen_page_flip()  local
1424 	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1426 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1428 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1431 	RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset);  in evergreen_page_flip()
1444 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in evergreen_page_flip_pending()  local
1447 	return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) &  in evergreen_page_flip_pending()
1675 	struct radeon_crtc *radeon_crtc;  in evergreen_pm_prepare()  local
1680 		radeon_crtc = to_radeon_crtc(crtc);  in evergreen_pm_prepare()
1681 		if (radeon_crtc->enabled) {  in evergreen_pm_prepare()
1682 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);  in evergreen_pm_prepare()
1684 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in evergreen_pm_prepare()
1700 	struct radeon_crtc *radeon_crtc;  in evergreen_pm_finish()  local
1705 		radeon_crtc = to_radeon_crtc(crtc);  in evergreen_pm_finish()
1706 		if (radeon_crtc->enabled) {  in evergreen_pm_finish()
1707 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);  in evergreen_pm_finish()
1709 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in evergreen_pm_finish()
1824 					struct radeon_crtc *radeon_crtc,  in evergreen_line_buffer_adjust()  argument
1829 	u32 pipe_offset = radeon_crtc->crtc_id * 0x20;  in evergreen_line_buffer_adjust()
1851 	if (radeon_crtc->base.enabled && mode) {  in evergreen_line_buffer_adjust()
1865 	if (radeon_crtc->crtc_id % 2)  in evergreen_line_buffer_adjust()
1867 	WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);  in evergreen_line_buffer_adjust()
1880 	if (radeon_crtc->base.enabled && mode) {  in evergreen_line_buffer_adjust()
2153 					 struct radeon_crtc *radeon_crtc,  in evergreen_program_watermarks()  argument
2156 	struct drm_display_mode *mode = &radeon_crtc->base.mode;  in evergreen_program_watermarks()
2165 	u32 pipe_offset = radeon_crtc->crtc_id * 16;  in evergreen_program_watermarks()
2169 	if (radeon_crtc->base.enabled && num_heads && mode) {  in evergreen_program_watermarks()
2197 		wm_high.vsc = radeon_crtc->vsc;  in evergreen_program_watermarks()
2199 		if (radeon_crtc->rmx_type != RMX_OFF)  in evergreen_program_watermarks()
2224 		wm_low.vsc = radeon_crtc->vsc;  in evergreen_program_watermarks()
2226 		if (radeon_crtc->rmx_type != RMX_OFF)  in evergreen_program_watermarks()
2260 		c.full = dfixed_mul(c, radeon_crtc->hsc);  in evergreen_program_watermarks()
2272 		c.full = dfixed_mul(c, radeon_crtc->hsc);  in evergreen_program_watermarks()
2280 		radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);  in evergreen_program_watermarks()
2304 	WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);  in evergreen_program_watermarks()
2305 	WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);  in evergreen_program_watermarks()
2308 	radeon_crtc->line_time = line_time;  in evergreen_program_watermarks()
2309 	radeon_crtc->wm_high = latency_watermark_a;  in evergreen_program_watermarks()
2310 	radeon_crtc->wm_low = latency_watermark_b;  in evergreen_program_watermarks()