Lines Matching refs:crtc_offset

1348 	WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);  in dce4_program_fmt()
1424 	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1426 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1428 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1431 	RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset);  in evergreen_page_flip()
1447 	return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) &  in evergreen_page_flip_pending()
1682 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);  in evergreen_pm_prepare()
1684 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in evergreen_pm_prepare()
1707 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);  in evergreen_pm_finish()
1709 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in evergreen_pm_finish()
1867 	WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);  in evergreen_line_buffer_adjust()
2304 	WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);  in evergreen_program_watermarks()
2305 	WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);  in evergreen_program_watermarks()