Lines Matching refs:RREG32
56 r = RREG32(EVERGREEN_CG_IND_DATA); in eg_cg_rreg()
78 r = RREG32(EVERGREEN_PIF_PHY0_DATA); in eg_pif_phy0_rreg()
100 r = RREG32(EVERGREEN_PIF_PHY1_DATA); in eg_pif_phy1_rreg()
1107 *val = RREG32(reg); in evergreen_get_allowed_info_register()
1159 if (RREG32(status_reg) & DCLK_STATUS) in sumo_set_uvd_clock()
1172 u32 cg_scratch = RREG32(CG_SCRATCH1); in sumo_set_uvd_clocks()
1353 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) in dce4_is_in_vblank()
1363 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1364 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1387 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) in dce4_wait_for_vblank()
1431 RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset); in evergreen_page_flip()
1447 return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & in evergreen_page_flip_pending()
1458 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >> in evergreen_get_temp()
1460 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >> in evergreen_get_temp()
1471 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> in evergreen_get_temp()
1492 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff; in sumo_get_temp()
1682 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_prepare()
1707 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_finish()
1728 return !!(RREG32(DC_HPDx_INT_STATUS_REG(hpd)) & DC_HPDx_SENSE); in evergreen_hpd_sense()
1873 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in evergreen_line_buffer_adjust()
1916 u32 tmp = RREG32(MC_SHARED_CHMAP); in evergreen_get_number_of_dram_channels()
2284 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks()
2293 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks()
2363 tmp = RREG32(SRBM_STATUS) & 0x1F00; in evergreen_mc_wait_for_idle()
2384 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); in evergreen_pcie_gart_tlb_flush()
2580 dig_fe = RREG32(NI_DIG_FE_CNTL + ni_dig_offsets[i]); in evergreen_is_dp_sst_stream_enabled()
2594 dig_be = RREG32(NI_DIG_BE_CNTL + ni_dig_offsets[i]); in evergreen_is_dp_sst_stream_enabled()
2601 dig_en_be = RREG32(NI_DIG_BE_EN_CNTL + in evergreen_is_dp_sst_stream_enabled()
2603 uniphy_pll = RREG32(NI_DCIO_UNIPHY0_PLL_CONTROL1 + in evergreen_is_dp_sst_stream_enabled()
2636 stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL + in evergreen_blank_dp_output()
2647 stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL + in evergreen_blank_dp_output()
2652 stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL + in evergreen_blank_dp_output()
2658 fifo_ctrl = RREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe]); in evergreen_blank_dp_output()
2671 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); in evergreen_mc_stop()
2672 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); in evergreen_mc_stop()
2679 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; in evergreen_mc_stop()
2683 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2692 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2721 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2734 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); in evergreen_mc_stop()
2748 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_stop()
2753 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); in evergreen_mc_stop()
2787 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]); in evergreen_mc_resume()
2792 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_resume()
2797 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); in evergreen_mc_resume()
2803 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_resume()
2812 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); in evergreen_mc_resume()
2821 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); in evergreen_mc_resume()
2827 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_resume()
2898 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF; in evergreen_mc_program()
3077 RREG32(GRBM_SOFT_RESET); in evergreen_cp_resume()
3080 RREG32(GRBM_SOFT_RESET); in evergreen_cp_resume()
3400 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); in evergreen_gpu_init()
3404 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG); in evergreen_gpu_init()
3406 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); in evergreen_gpu_init()
3467 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; in evergreen_gpu_init()
3488 simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; in evergreen_gpu_init()
3539 sx_debug_1 = RREG32(SX_DEBUG_1); in evergreen_gpu_init()
3544 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); in evergreen_gpu_init()
3570 sq_config = RREG32(SQ_CONFIG); in evergreen_gpu_init()
3595 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT); in evergreen_gpu_init()
3697 tmp = RREG32(HDP_MISC_CNTL); in evergreen_gpu_init()
3701 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); in evergreen_gpu_init()
3720 tmp = RREG32(FUS_MC_ARB_RAMCFG); in evergreen_mc_init()
3722 tmp = RREG32(MC_ARB_RAMCFG); in evergreen_mc_init()
3730 tmp = RREG32(MC_SHARED_CHMAP); in evergreen_mc_init()
3755 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in evergreen_mc_init()
3756 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in evergreen_mc_init()
3759 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in evergreen_mc_init()
3760 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in evergreen_mc_init()
3772 RREG32(GRBM_STATUS)); in evergreen_print_gpu_status_regs()
3774 RREG32(GRBM_STATUS_SE0)); in evergreen_print_gpu_status_regs()
3776 RREG32(GRBM_STATUS_SE1)); in evergreen_print_gpu_status_regs()
3778 RREG32(SRBM_STATUS)); in evergreen_print_gpu_status_regs()
3780 RREG32(SRBM_STATUS2)); in evergreen_print_gpu_status_regs()
3782 RREG32(CP_STALLED_STAT1)); in evergreen_print_gpu_status_regs()
3784 RREG32(CP_STALLED_STAT2)); in evergreen_print_gpu_status_regs()
3786 RREG32(CP_BUSY_STAT)); in evergreen_print_gpu_status_regs()
3788 RREG32(CP_STAT)); in evergreen_print_gpu_status_regs()
3790 RREG32(DMA_STATUS_REG)); in evergreen_print_gpu_status_regs()
3793 RREG32(DMA_STATUS_REG + 0x800)); in evergreen_print_gpu_status_regs()
3804 if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) { in evergreen_is_display_hung()
3805 crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in evergreen_is_display_hung()
3813 tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in evergreen_is_display_hung()
3832 tmp = RREG32(GRBM_STATUS); in evergreen_gpu_check_soft_reset()
3848 tmp = RREG32(DMA_STATUS_REG); in evergreen_gpu_check_soft_reset()
3853 tmp = RREG32(SRBM_STATUS2); in evergreen_gpu_check_soft_reset()
3858 tmp = RREG32(SRBM_STATUS); in evergreen_gpu_check_soft_reset()
3882 tmp = RREG32(VM_L2_STATUS); in evergreen_gpu_check_soft_reset()
3913 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_soft_reset()
3973 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
3977 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
3983 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
3987 tmp = RREG32(SRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
3991 tmp = RREG32(SRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
3997 tmp = RREG32(SRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4022 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_pci_config_reset()
4045 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) in evergreen_gpu_pci_config_reset()
4398 u32 tmp = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; in evergreen_rlc_resume()
4455 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in evergreen_get_vblank_counter()
4468 tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state()
4472 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state()
4513 thermal_int = RREG32(TN_CG_THERMAL_INT_CTRL) & in evergreen_irq_set()
4516 thermal_int = RREG32(CG_THERMAL_INT) & in evergreen_irq_set()
4519 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_irq_set()
4549 dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; in evergreen_irq_set()
4606 RREG32(SRBM_STATUS); in evergreen_irq_set()
4620 disp_int[i] = RREG32(evergreen_disp_int_status[i]); in evergreen_irq_ack()
4621 afmt_status[i] = RREG32(AFMT_STATUS + crtc_offsets[i]); in evergreen_irq_ack()
4623 grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]); in evergreen_irq_ack()
4683 wptr = RREG32(IH_RB_WPTR); in evergreen_get_ih_wptr()
4694 tmp = RREG32(IH_RB_CNTL); in evergreen_get_ih_wptr()
4835 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); in evergreen_irq_process()
4844 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); in evergreen_irq_process()
4845 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS); in evergreen_irq_process()