Lines Matching refs:WREG32
194 WREG32(CIK_DIDT_IND_INDEX, (reg)); in cik_didt_rreg()
205 WREG32(CIK_DIDT_IND_INDEX, (reg)); in cik_didt_wreg()
206 WREG32(CIK_DIDT_IND_DATA, (v)); in cik_didt_wreg()
252 WREG32(PCIE_INDEX, reg); in cik_pciep_rreg()
264 WREG32(PCIE_INDEX, reg); in cik_pciep_wreg()
266 WREG32(PCIE_DATA, v); in cik_pciep_wreg()
1857 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl); in cik_srbm_select()
1915 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ci_mc_load_microcode()
1916 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in ci_mc_load_microcode()
1921 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in ci_mc_load_microcode()
1922 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); in ci_mc_load_microcode()
1924 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); in ci_mc_load_microcode()
1925 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); in ci_mc_load_microcode()
1931 WREG32(MC_SEQ_IO_DEBUG_INDEX, 5); in ci_mc_load_microcode()
1932 WREG32(MC_SEQ_IO_DEBUG_DATA, 0x00000023); in ci_mc_load_microcode()
1933 WREG32(MC_SEQ_IO_DEBUG_INDEX, 9); in ci_mc_load_microcode()
1934 WREG32(MC_SEQ_IO_DEBUG_DATA, 0x000001f0); in ci_mc_load_microcode()
1940 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); in ci_mc_load_microcode()
1942 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); in ci_mc_load_microcode()
1946 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ci_mc_load_microcode()
1947 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); in ci_mc_load_microcode()
1948 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); in ci_mc_load_microcode()
2503 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in cik_tiling_mode_table_init()
2505 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); in cik_tiling_mode_table_init()
2646 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in cik_tiling_mode_table_init()
2648 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); in cik_tiling_mode_table_init()
2871 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in cik_tiling_mode_table_init()
2873 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); in cik_tiling_mode_table_init()
3014 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in cik_tiling_mode_table_init()
3016 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); in cik_tiling_mode_table_init()
3048 WREG32(GRBM_GFX_INDEX, data); in cik_select_se_sh()
3165 WREG32(PA_SC_RASTER_CONFIG, data); in cik_setup_rb()
3261 WREG32((0x2c14 + j), 0x00000000); in cik_gpu_init()
3262 WREG32((0x2c18 + j), 0x00000000); in cik_gpu_init()
3263 WREG32((0x2c1c + j), 0x00000000); in cik_gpu_init()
3264 WREG32((0x2c20 + j), 0x00000000); in cik_gpu_init()
3265 WREG32((0x2c24 + j), 0x00000000); in cik_gpu_init()
3268 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in cik_gpu_init()
3269 WREG32(SRBM_INT_CNTL, 0x1); in cik_gpu_init()
3270 WREG32(SRBM_INT_ACK, 0x1); in cik_gpu_init()
3272 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); in cik_gpu_init()
3334 WREG32(GB_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3335 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3336 WREG32(DMIF_ADDR_CALC, gb_addr_config); in cik_gpu_init()
3337 WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
3338 WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
3339 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3340 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3341 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3358 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); in cik_gpu_init()
3360 WREG32(SX_DEBUG_1, 0x20); in cik_gpu_init()
3362 WREG32(TA_CNTL_AUX, 0x00010000); in cik_gpu_init()
3366 WREG32(SPI_CONFIG_CNTL, tmp); in cik_gpu_init()
3368 WREG32(SQ_CONFIG, 1); in cik_gpu_init()
3370 WREG32(DB_DEBUG, 0); in cik_gpu_init()
3374 WREG32(DB_DEBUG2, tmp); in cik_gpu_init()
3378 WREG32(DB_DEBUG3, tmp); in cik_gpu_init()
3382 WREG32(CB_HW_CONTROL, tmp); in cik_gpu_init()
3384 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); in cik_gpu_init()
3386 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) | in cik_gpu_init()
3391 WREG32(VGT_NUM_INSTANCES, 1); in cik_gpu_init()
3393 WREG32(CP_PERFMON_CNTL, 0); in cik_gpu_init()
3395 WREG32(SQ_CONFIG, 0); in cik_gpu_init()
3397 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | in cik_gpu_init()
3400 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | in cik_gpu_init()
3403 WREG32(VGT_GS_VERTEX_REUSE, 16); in cik_gpu_init()
3404 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in cik_gpu_init()
3408 WREG32(HDP_MISC_CNTL, tmp); in cik_gpu_init()
3411 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); in cik_gpu_init()
3413 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); in cik_gpu_init()
3414 WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER); in cik_gpu_init()
3467 WREG32(scratch, 0xCAFEDEAD); in cik_ring_test()
3792 WREG32(scratch, 0xCAFEDEAD); in cik_ib_test()
3876 WREG32(CP_ME_CNTL, 0); in cik_cp_gfx_enable()
3880 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in cik_cp_gfx_enable()
3921 WREG32(CP_PFP_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3923 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3924 WREG32(CP_PFP_UCODE_ADDR, le32_to_cpu(pfp_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
3930 WREG32(CP_CE_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3932 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3933 WREG32(CP_CE_UCODE_ADDR, le32_to_cpu(ce_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
3939 WREG32(CP_ME_RAM_WADDR, 0); in cik_cp_gfx_load_microcode()
3941 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3942 WREG32(CP_ME_RAM_WADDR, le32_to_cpu(me_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
3943 WREG32(CP_ME_RAM_RADDR, le32_to_cpu(me_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
3949 WREG32(CP_PFP_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3951 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3952 WREG32(CP_PFP_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3956 WREG32(CP_CE_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3958 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3959 WREG32(CP_CE_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3963 WREG32(CP_ME_RAM_WADDR, 0); in cik_cp_gfx_load_microcode()
3965 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3966 WREG32(CP_ME_RAM_WADDR, 0); in cik_cp_gfx_load_microcode()
3987 WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1); in cik_cp_gfx_start()
3988 WREG32(CP_ENDIAN_SWAP, 0); in cik_cp_gfx_start()
3989 WREG32(CP_DEVICE_ID, 1); in cik_cp_gfx_start()
4064 WREG32(CP_SEM_WAIT_TIMER, 0x0); in cik_cp_gfx_resume()
4066 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in cik_cp_gfx_resume()
4069 WREG32(CP_RB_WPTR_DELAY, 0); in cik_cp_gfx_resume()
4072 WREG32(CP_RB_VMID, 0); in cik_cp_gfx_resume()
4074 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in cik_cp_gfx_resume()
4084 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4087 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in cik_cp_gfx_resume()
4089 WREG32(CP_RB0_WPTR, ring->wptr); in cik_cp_gfx_resume()
4092 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); in cik_cp_gfx_resume()
4093 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in cik_cp_gfx_resume()
4096 WREG32(SCRATCH_UMSK, 0); in cik_cp_gfx_resume()
4102 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4105 WREG32(CP_RB0_BASE, rb_addr); in cik_cp_gfx_resume()
4106 WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr)); in cik_cp_gfx_resume()
4145 WREG32(CP_RB0_WPTR, ring->wptr); in cik_gfx_set_wptr()
4203 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp); in cik_compute_stop()
4206 WREG32(CP_HQD_DEQUEUE_REQUEST, 1); in cik_compute_stop()
4212 WREG32(CP_HQD_DEQUEUE_REQUEST, 0); in cik_compute_stop()
4213 WREG32(CP_HQD_PQ_RPTR, 0); in cik_compute_stop()
4214 WREG32(CP_HQD_PQ_WPTR, 0); in cik_compute_stop()
4230 WREG32(CP_MEC_CNTL, 0); in cik_cp_compute_enable()
4241 WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT)); in cik_cp_compute_enable()
4277 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4279 WREG32(CP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4280 WREG32(CP_MEC_ME1_UCODE_ADDR, le32_to_cpu(mec_hdr->header.ucode_version)); in cik_cp_compute_load_microcode()
4291 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4293 WREG32(CP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4294 WREG32(CP_MEC_ME2_UCODE_ADDR, le32_to_cpu(mec2_hdr->header.ucode_version)); in cik_cp_compute_load_microcode()
4301 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4303 WREG32(CP_MEC_ME1_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4304 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4309 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4311 WREG32(CP_MEC_ME2_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4312 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4537 WREG32(CP_CPF_DEBUG, tmp); in cik_cp_compute_resume()
4550 WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); in cik_cp_compute_resume()
4551 WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); in cik_cp_compute_resume()
4554 WREG32(CP_HPD_EOP_VMID, 0); in cik_cp_compute_resume()
4560 WREG32(CP_HPD_EOP_CONTROL, tmp); in cik_cp_compute_resume()
4622 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp); in cik_cp_compute_resume()
4631 WREG32(CP_HQD_PQ_DOORBELL_CONTROL, in cik_cp_compute_resume()
4639 WREG32(CP_HQD_DEQUEUE_REQUEST, 1); in cik_cp_compute_resume()
4645 WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request); in cik_cp_compute_resume()
4646 WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr); in cik_cp_compute_resume()
4647 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); in cik_cp_compute_resume()
4653 WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr); in cik_cp_compute_resume()
4654 WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi); in cik_cp_compute_resume()
4658 WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control); in cik_cp_compute_resume()
4664 WREG32(CP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base); in cik_cp_compute_resume()
4665 WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi); in cik_cp_compute_resume()
4683 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); in cik_cp_compute_resume()
4692 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr); in cik_cp_compute_resume()
4693 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR_HI, in cik_cp_compute_resume()
4704 WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR, in cik_cp_compute_resume()
4706 WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR_HI, in cik_cp_compute_resume()
4723 WREG32(CP_HQD_PQ_DOORBELL_CONTROL, in cik_cp_compute_resume()
4729 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); in cik_cp_compute_resume()
4734 WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid); in cik_cp_compute_resume()
4738 WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active); in cik_cp_compute_resume()
4957 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_soft_reset()
4960 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); in cik_gpu_soft_reset()
4966 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
4972 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
5022 WREG32(GRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5028 WREG32(GRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5036 WREG32(SRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5042 WREG32(SRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5068 WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP); in kv_save_regs_for_reset()
5069 WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE | in kv_save_regs_for_reset()
5078 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5079 WREG32(GMCON_PGFSM_CONFIG, 0x200010ff); in kv_restore_regs_for_reset()
5082 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5084 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5085 WREG32(GMCON_PGFSM_CONFIG, 0x300010ff); in kv_restore_regs_for_reset()
5088 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5090 WREG32(GMCON_PGFSM_WRITE, 0x210000); in kv_restore_regs_for_reset()
5091 WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff); in kv_restore_regs_for_reset()
5094 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5096 WREG32(GMCON_PGFSM_WRITE, 0x21003); in kv_restore_regs_for_reset()
5097 WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff); in kv_restore_regs_for_reset()
5100 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5102 WREG32(GMCON_PGFSM_WRITE, 0x2b00); in kv_restore_regs_for_reset()
5103 WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff); in kv_restore_regs_for_reset()
5106 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5108 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5109 WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff); in kv_restore_regs_for_reset()
5112 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5114 WREG32(GMCON_PGFSM_WRITE, 0x420000); in kv_restore_regs_for_reset()
5115 WREG32(GMCON_PGFSM_CONFIG, 0x100010ff); in kv_restore_regs_for_reset()
5118 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5120 WREG32(GMCON_PGFSM_WRITE, 0x120202); in kv_restore_regs_for_reset()
5121 WREG32(GMCON_PGFSM_CONFIG, 0x500010ff); in kv_restore_regs_for_reset()
5124 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5126 WREG32(GMCON_PGFSM_WRITE, 0x3e3e36); in kv_restore_regs_for_reset()
5127 WREG32(GMCON_PGFSM_CONFIG, 0x600010ff); in kv_restore_regs_for_reset()
5130 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5132 WREG32(GMCON_PGFSM_WRITE, 0x373f3e); in kv_restore_regs_for_reset()
5133 WREG32(GMCON_PGFSM_CONFIG, 0x700010ff); in kv_restore_regs_for_reset()
5136 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5138 WREG32(GMCON_PGFSM_WRITE, 0x3e1332); in kv_restore_regs_for_reset()
5139 WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff); in kv_restore_regs_for_reset()
5141 WREG32(GMCON_MISC3, save->gmcon_misc3); in kv_restore_regs_for_reset()
5142 WREG32(GMCON_MISC, save->gmcon_misc); in kv_restore_regs_for_reset()
5143 WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute); in kv_restore_regs_for_reset()
5161 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_pci_config_reset()
5164 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); in cik_gpu_pci_config_reset()
5169 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
5173 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
5289 WREG32((0x2c14 + j), 0x00000000); in cik_mc_program()
5290 WREG32((0x2c18 + j), 0x00000000); in cik_mc_program()
5291 WREG32((0x2c1c + j), 0x00000000); in cik_mc_program()
5292 WREG32((0x2c20 + j), 0x00000000); in cik_mc_program()
5293 WREG32((0x2c24 + j), 0x00000000); in cik_mc_program()
5295 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); in cik_mc_program()
5302 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in cik_mc_program()
5304 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in cik_mc_program()
5306 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in cik_mc_program()
5308 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, in cik_mc_program()
5312 WREG32(MC_VM_FB_LOCATION, tmp); in cik_mc_program()
5314 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in cik_mc_program()
5315 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); in cik_mc_program()
5316 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); in cik_mc_program()
5317 WREG32(MC_VM_AGP_BASE, 0); in cik_mc_program()
5318 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); in cik_mc_program()
5319 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); in cik_mc_program()
5412 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0); in cik_pcie_gart_tlb_flush()
5415 WREG32(VM_INVALIDATE_REQUEST, 0x1); in cik_pcie_gart_tlb_flush()
5441 WREG32(MC_VM_MX_L1_TLB_CNTL, in cik_pcie_gart_enable()
5449 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in cik_pcie_gart_enable()
5455 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cik_pcie_gart_enable()
5456 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_enable()
5460 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in cik_pcie_gart_enable()
5461 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in cik_pcie_gart_enable()
5462 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in cik_pcie_gart_enable()
5463 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in cik_pcie_gart_enable()
5465 WREG32(VM_CONTEXT0_CNTL2, 0); in cik_pcie_gart_enable()
5466 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cik_pcie_gart_enable()
5469 WREG32(0x15D4, 0); in cik_pcie_gart_enable()
5470 WREG32(0x15D8, 0); in cik_pcie_gart_enable()
5471 WREG32(0x15DC, 0); in cik_pcie_gart_enable()
5475 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); in cik_pcie_gart_enable()
5476 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1); in cik_pcie_gart_enable()
5479 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), in cik_pcie_gart_enable()
5482 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), in cik_pcie_gart_enable()
5487 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, in cik_pcie_gart_enable()
5489 WREG32(VM_CONTEXT1_CNTL2, 4); in cik_pcie_gart_enable()
5490 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cik_pcie_gart_enable()
5508 WREG32(CHUB_CONTROL, tmp); in cik_pcie_gart_enable()
5517 WREG32(SH_MEM_CONFIG, SH_MEM_CONFIG_GFX_DEFAULT); in cik_pcie_gart_enable()
5518 WREG32(SH_MEM_APE1_BASE, 1); in cik_pcie_gart_enable()
5519 WREG32(SH_MEM_APE1_LIMIT, 0); in cik_pcie_gart_enable()
5520 WREG32(SH_MEM_BASES, 0); in cik_pcie_gart_enable()
5522 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5523 WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5524 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5525 WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5560 WREG32(VM_CONTEXT0_CNTL, 0); in cik_pcie_gart_disable()
5561 WREG32(VM_CONTEXT1_CNTL, 0); in cik_pcie_gart_disable()
5563 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | in cik_pcie_gart_disable()
5566 WREG32(VM_L2_CNTL, in cik_pcie_gart_disable()
5572 WREG32(VM_L2_CNTL2, 0); in cik_pcie_gart_disable()
5573 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_disable()
5777 WREG32(CP_INT_CNTL_RING0, tmp); in cik_enable_gui_idle_interrupt()
5789 WREG32(RLC_LB_CNTL, tmp); in cik_enable_lbpw()
5823 WREG32(RLC_CNTL, rlc); in cik_update_rlc()
5836 WREG32(RLC_CNTL, data); in cik_halt_rlc()
5855 WREG32(RLC_GPR_REG2, tmp); in cik_enter_rlc_safe_mode()
5876 WREG32(RLC_GPR_REG2, tmp); in cik_exit_rlc_safe_mode()
5888 WREG32(RLC_CNTL, 0); in cik_rlc_stop()
5904 WREG32(RLC_CNTL, RLC_ENABLE); in cik_rlc_start()
5931 WREG32(RLC_CGCG_CGLS_CTRL, tmp); in cik_rlc_resume()
5939 WREG32(RLC_LB_CNTR_INIT, 0); in cik_rlc_resume()
5940 WREG32(RLC_LB_CNTR_MAX, 0x00008000); in cik_rlc_resume()
5943 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff); in cik_rlc_resume()
5944 WREG32(RLC_LB_PARAMS, 0x00600408); in cik_rlc_resume()
5945 WREG32(RLC_LB_CNTL, 0x80000004); in cik_rlc_resume()
5947 WREG32(RLC_MC_CNTL, 0); in cik_rlc_resume()
5948 WREG32(RLC_UCODE_CNTL, 0); in cik_rlc_resume()
5959 WREG32(RLC_GPM_UCODE_ADDR, 0); in cik_rlc_resume()
5961 WREG32(RLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_rlc_resume()
5962 WREG32(RLC_GPM_UCODE_ADDR, le32_to_cpu(hdr->header.ucode_version)); in cik_rlc_resume()
5984 WREG32(RLC_GPM_UCODE_ADDR, 0); in cik_rlc_resume()
5986 WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_rlc_resume()
5987 WREG32(RLC_GPM_UCODE_ADDR, 0); in cik_rlc_resume()
5994 WREG32(RLC_DRIVER_DMA_STATUS, 0); in cik_rlc_resume()
6013 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in cik_enable_cgcg()
6014 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in cik_enable_cgcg()
6016 WREG32(RLC_SERDES_WR_CTRL, tmp2); in cik_enable_cgcg()
6033 WREG32(RLC_CGCG_CGLS_CTRL, data); in cik_enable_cgcg()
6047 WREG32(CP_MEM_SLP_CNTL, data); in cik_enable_mgcg()
6055 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); in cik_enable_mgcg()
6060 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6061 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6063 WREG32(RLC_SERDES_WR_CTRL, data); in cik_enable_mgcg()
6080 WREG32(CGTS_SM_CTRL_REG, data); in cik_enable_mgcg()
6086 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); in cik_enable_mgcg()
6091 WREG32(RLC_MEM_SLP_CNTL, data); in cik_enable_mgcg()
6097 WREG32(CP_MEM_SLP_CNTL, data); in cik_enable_mgcg()
6103 WREG32(CGTS_SM_CTRL_REG, data); in cik_enable_mgcg()
6108 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6109 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6111 WREG32(RLC_SERDES_WR_CTRL, data); in cik_enable_mgcg()
6143 WREG32(mc_cg_registers[i], data); in cik_enable_mc_ls()
6160 WREG32(mc_cg_registers[i], data); in cik_enable_mc_mgcg()
6170 WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
6171 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
6176 WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
6181 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
6194 WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6199 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6204 WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6209 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6226 WREG32(UVD_CGC_CTRL, data); in cik_enable_uvd_mgcg()
6235 WREG32(UVD_CGC_CTRL, data); in cik_enable_uvd_mgcg()
6270 WREG32(HDP_HOST_PATH_CNTL, data); in cik_enable_hdp_mgcg()
6286 WREG32(HDP_MEM_POWER_LS, data); in cik_enable_hdp_ls()
6374 WREG32(RLC_PG_CNTL, data); in cik_enable_sck_slowdown_on_pu()
6388 WREG32(RLC_PG_CNTL, data); in cik_enable_sck_slowdown_on_pd()
6401 WREG32(RLC_PG_CNTL, data); in cik_enable_cp_pg()
6414 WREG32(RLC_PG_CNTL, data); in cik_enable_gds_pg()
6514 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_cgpg()
6519 WREG32(RLC_AUTO_PG_CTRL, data); in cik_enable_gfx_cgpg()
6524 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_cgpg()
6529 WREG32(RLC_AUTO_PG_CTRL, data); in cik_enable_gfx_cgpg()
6583 WREG32(RLC_PG_AO_CU_MASK, tmp); in cik_init_ao_cu_mask()
6588 WREG32(RLC_MAX_PG_CU, tmp); in cik_init_ao_cu_mask()
6602 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_static_mgpg()
6616 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_dynamic_mgpg()
6628 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); in cik_init_gfx_cgpg()
6629 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6630 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6631 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size); in cik_init_gfx_cgpg()
6633 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); in cik_init_gfx_cgpg()
6635 WREG32(RLC_GPM_SCRATCH_DATA, 0); in cik_init_gfx_cgpg()
6638 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); in cik_init_gfx_cgpg()
6640 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]); in cik_init_gfx_cgpg()
6646 WREG32(RLC_PG_CNTL, data); in cik_init_gfx_cgpg()
6648 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in cik_init_gfx_cgpg()
6649 WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8); in cik_init_gfx_cgpg()
6654 WREG32(CP_RB_WPTR_POLL_CNTL, data); in cik_init_gfx_cgpg()
6657 WREG32(RLC_PG_DELAY, data); in cik_init_gfx_cgpg()
6662 WREG32(RLC_PG_DELAY_2, data); in cik_init_gfx_cgpg()
6667 WREG32(RLC_AUTO_PG_CTRL, data); in cik_init_gfx_cgpg()
6830 WREG32(IH_CNTL, ih_cntl); in cik_enable_interrupts()
6831 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_enable_interrupts()
6849 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_disable_interrupts()
6850 WREG32(IH_CNTL, ih_cntl); in cik_disable_interrupts()
6852 WREG32(IH_RB_RPTR, 0); in cik_disable_interrupts()
6853 WREG32(IH_RB_WPTR, 0); in cik_disable_interrupts()
6872 WREG32(CP_INT_CNTL_RING0, tmp); in cik_disable_interrupt_state()
6875 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
6877 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
6879 WREG32(CP_ME1_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
6880 WREG32(CP_ME1_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state()
6881 WREG32(CP_ME1_PIPE2_INT_CNTL, 0); in cik_disable_interrupt_state()
6882 WREG32(CP_ME1_PIPE3_INT_CNTL, 0); in cik_disable_interrupt_state()
6883 WREG32(CP_ME2_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
6884 WREG32(CP_ME2_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state()
6885 WREG32(CP_ME2_PIPE2_INT_CNTL, 0); in cik_disable_interrupt_state()
6886 WREG32(CP_ME2_PIPE3_INT_CNTL, 0); in cik_disable_interrupt_state()
6888 WREG32(GRBM_INT_CNTL, 0); in cik_disable_interrupt_state()
6890 WREG32(SRBM_INT_CNTL, 0); in cik_disable_interrupt_state()
6892 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6893 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6895 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6896 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6899 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6900 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6904 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6905 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6908 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6909 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6912 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6913 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6917 WREG32(DAC_AUTODETECT_INT_CONTROL, 0); in cik_disable_interrupt_state()
6921 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_disable_interrupt_state()
6923 WREG32(DC_HPD2_INT_CONTROL, tmp); in cik_disable_interrupt_state()
6925 WREG32(DC_HPD3_INT_CONTROL, tmp); in cik_disable_interrupt_state()
6927 WREG32(DC_HPD4_INT_CONTROL, tmp); in cik_disable_interrupt_state()
6929 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_disable_interrupt_state()
6931 WREG32(DC_HPD6_INT_CONTROL, tmp); in cik_disable_interrupt_state()
6969 WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8); in cik_irq_init()
6977 WREG32(INTERRUPT_CNTL, interrupt_cntl); in cik_irq_init()
6979 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in cik_irq_init()
6990 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in cik_irq_init()
6991 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in cik_irq_init()
6993 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_irq_init()
6996 WREG32(IH_RB_RPTR, 0); in cik_irq_init()
6997 WREG32(IH_RB_WPTR, 0); in cik_irq_init()
7004 WREG32(IH_CNTL, ih_cntl); in cik_irq_init()
7228 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()
7230 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl); in cik_irq_set()
7231 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1); in cik_irq_set()
7233 WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0); in cik_irq_set()
7234 WREG32(CP_ME1_PIPE1_INT_CNTL, cp_m1p1); in cik_irq_set()
7235 WREG32(CP_ME1_PIPE2_INT_CNTL, cp_m1p2); in cik_irq_set()
7236 WREG32(CP_ME1_PIPE3_INT_CNTL, cp_m1p3); in cik_irq_set()
7237 WREG32(CP_ME2_PIPE0_INT_CNTL, cp_m2p0); in cik_irq_set()
7238 WREG32(CP_ME2_PIPE1_INT_CNTL, cp_m2p1); in cik_irq_set()
7239 WREG32(CP_ME2_PIPE2_INT_CNTL, cp_m2p2); in cik_irq_set()
7240 WREG32(CP_ME2_PIPE3_INT_CNTL, cp_m2p3); in cik_irq_set()
7242 WREG32(GRBM_INT_CNTL, grbm_int_cntl); in cik_irq_set()
7244 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); in cik_irq_set()
7245 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in cik_irq_set()
7247 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); in cik_irq_set()
7248 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); in cik_irq_set()
7251 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); in cik_irq_set()
7252 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in cik_irq_set()
7256 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in cik_irq_set()
7258 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_set()
7262 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_set()
7264 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_set()
7268 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_set()
7270 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, in cik_irq_set()
7274 WREG32(DC_HPD1_INT_CONTROL, hpd1); in cik_irq_set()
7275 WREG32(DC_HPD2_INT_CONTROL, hpd2); in cik_irq_set()
7276 WREG32(DC_HPD3_INT_CONTROL, hpd3); in cik_irq_set()
7277 WREG32(DC_HPD4_INT_CONTROL, hpd4); in cik_irq_set()
7278 WREG32(DC_HPD5_INT_CONTROL, hpd5); in cik_irq_set()
7279 WREG32(DC_HPD6_INT_CONTROL, hpd6); in cik_irq_set()
7326 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, in cik_irq_ack()
7329 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_ack()
7332 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7334 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7336 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7338 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7342 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_ack()
7345 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_ack()
7348 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7350 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7352 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7354 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7359 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_ack()
7362 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, in cik_irq_ack()
7365 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7367 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7369 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7371 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7377 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_irq_ack()
7382 WREG32(DC_HPD2_INT_CONTROL, tmp); in cik_irq_ack()
7387 WREG32(DC_HPD3_INT_CONTROL, tmp); in cik_irq_ack()
7392 WREG32(DC_HPD4_INT_CONTROL, tmp); in cik_irq_ack()
7397 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_irq_ack()
7402 WREG32(DC_HPD6_INT_CONTROL, tmp); in cik_irq_ack()
7407 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_irq_ack()
7412 WREG32(DC_HPD2_INT_CONTROL, tmp); in cik_irq_ack()
7417 WREG32(DC_HPD3_INT_CONTROL, tmp); in cik_irq_ack()
7422 WREG32(DC_HPD4_INT_CONTROL, tmp); in cik_irq_ack()
7427 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_irq_ack()
7432 WREG32(DC_HPD6_INT_CONTROL, tmp); in cik_irq_ack()
7512 WREG32(IH_RB_CNTL, tmp); in cik_get_ih_wptr()
7899 WREG32(SRBM_INT_ACK, 0x1); in cik_irq_process()
8098 WREG32(IH_RB_RPTR, rptr); in cik_irq_process()
8801 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_fmt()
8851 WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset, in dce8_line_buffer_adjust()
8854 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce8_line_buffer_adjust()
9353 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_watermarks()
9354 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce8_program_watermarks()
9361 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_watermarks()
9362 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce8_program_watermarks()
9366 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask); in dce8_program_watermarks()
9417 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); in cik_get_gpu_clock_counter()