Lines Matching refs:RREG32
178 *val = RREG32(reg); in cik_get_allowed_info_register()
195 r = RREG32(CIK_DIDT_IND_DATA); in cik_didt_rreg()
253 (void)RREG32(PCIE_INDEX); in cik_pciep_rreg()
254 r = RREG32(PCIE_DATA); in cik_pciep_rreg()
265 (void)RREG32(PCIE_INDEX); in cik_pciep_wreg()
267 (void)RREG32(PCIE_DATA); in cik_pciep_wreg()
1911 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; in ci_mc_load_microcode()
1929 tmp = RREG32(MC_SEQ_MISC0); in ci_mc_load_microcode()
1952 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) in ci_mc_load_microcode()
1957 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) in ci_mc_load_microcode()
3087 data = RREG32(CC_RB_BACKEND_DISABLE); in cik_get_rb_disabled()
3092 data |= RREG32(GC_USER_RB_BACKEND_DISABLE); in cik_get_rb_disabled()
3180 u32 gb_addr_config = RREG32(GB_ADDR_CONFIG); in cik_gpu_init()
3274 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); in cik_gpu_init()
3275 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); in cik_gpu_init()
3364 tmp = RREG32(SPI_CONFIG_CNTL); in cik_gpu_init()
3372 tmp = RREG32(DB_DEBUG2) & ~0xf00fffff; in cik_gpu_init()
3376 tmp = RREG32(DB_DEBUG3) & ~0x0002021c; in cik_gpu_init()
3380 tmp = RREG32(CB_HW_CONTROL) & ~0x00010000; in cik_gpu_init()
3406 tmp = RREG32(HDP_MISC_CNTL); in cik_gpu_init()
3410 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); in cik_gpu_init()
3480 tmp = RREG32(scratch); in cik_ring_test()
3825 tmp = RREG32(scratch); in cik_ib_test()
4131 rptr = RREG32(CP_RB0_RPTR); in cik_gfx_get_rptr()
4139 return RREG32(CP_RB0_WPTR); in cik_gfx_get_wptr()
4146 (void)RREG32(CP_RB0_WPTR); in cik_gfx_set_wptr()
4159 rptr = RREG32(CP_HQD_PQ_RPTR); in cik_compute_get_rptr()
4178 wptr = RREG32(CP_HQD_PQ_WPTR); in cik_compute_get_wptr()
4201 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL); in cik_compute_stop()
4205 if (RREG32(CP_HQD_ACTIVE) & 1) { in cik_compute_stop()
4208 if (!(RREG32(CP_HQD_ACTIVE) & 1)) in cik_compute_stop()
4535 tmp = RREG32(CP_CPF_DEBUG); in cik_cp_compute_resume()
4557 tmp = RREG32(CP_HPD_EOP_CONTROL); in cik_cp_compute_resume()
4620 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL); in cik_cp_compute_resume()
4626 RREG32(CP_HQD_PQ_DOORBELL_CONTROL); in cik_cp_compute_resume()
4638 if (RREG32(CP_HQD_ACTIVE) & 1) { in cik_cp_compute_resume()
4641 if (!(RREG32(CP_HQD_ACTIVE) & 1)) in cik_cp_compute_resume()
4656 mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL); in cik_cp_compute_resume()
4668 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL); in cik_cp_compute_resume()
4712 RREG32(CP_HQD_PQ_DOORBELL_CONTROL); in cik_cp_compute_resume()
4730 mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR); in cik_cp_compute_resume()
4806 RREG32(GRBM_STATUS)); in cik_print_gpu_status_regs()
4808 RREG32(GRBM_STATUS2)); in cik_print_gpu_status_regs()
4810 RREG32(GRBM_STATUS_SE0)); in cik_print_gpu_status_regs()
4812 RREG32(GRBM_STATUS_SE1)); in cik_print_gpu_status_regs()
4814 RREG32(GRBM_STATUS_SE2)); in cik_print_gpu_status_regs()
4816 RREG32(GRBM_STATUS_SE3)); in cik_print_gpu_status_regs()
4818 RREG32(SRBM_STATUS)); in cik_print_gpu_status_regs()
4820 RREG32(SRBM_STATUS2)); in cik_print_gpu_status_regs()
4822 RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); in cik_print_gpu_status_regs()
4824 RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); in cik_print_gpu_status_regs()
4825 dev_info(rdev->dev, " CP_STAT = 0x%08x\n", RREG32(CP_STAT)); in cik_print_gpu_status_regs()
4827 RREG32(CP_STALLED_STAT1)); in cik_print_gpu_status_regs()
4829 RREG32(CP_STALLED_STAT2)); in cik_print_gpu_status_regs()
4831 RREG32(CP_STALLED_STAT3)); in cik_print_gpu_status_regs()
4833 RREG32(CP_CPF_BUSY_STAT)); in cik_print_gpu_status_regs()
4835 RREG32(CP_CPF_STALLED_STAT1)); in cik_print_gpu_status_regs()
4836 dev_info(rdev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(CP_CPF_STATUS)); in cik_print_gpu_status_regs()
4837 dev_info(rdev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(CP_CPC_BUSY_STAT)); in cik_print_gpu_status_regs()
4839 RREG32(CP_CPC_STALLED_STAT1)); in cik_print_gpu_status_regs()
4840 dev_info(rdev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(CP_CPC_STATUS)); in cik_print_gpu_status_regs()
4858 tmp = RREG32(GRBM_STATUS); in cik_gpu_check_soft_reset()
4871 tmp = RREG32(GRBM_STATUS2); in cik_gpu_check_soft_reset()
4876 tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET); in cik_gpu_check_soft_reset()
4881 tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); in cik_gpu_check_soft_reset()
4886 tmp = RREG32(SRBM_STATUS2); in cik_gpu_check_soft_reset()
4894 tmp = RREG32(SRBM_STATUS); in cik_gpu_check_soft_reset()
4945 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); in cik_gpu_soft_reset()
4947 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); in cik_gpu_soft_reset()
4964 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_soft_reset()
4970 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_soft_reset()
5019 tmp = RREG32(GRBM_SOFT_RESET); in cik_gpu_soft_reset()
5023 tmp = RREG32(GRBM_SOFT_RESET); in cik_gpu_soft_reset()
5029 tmp = RREG32(GRBM_SOFT_RESET); in cik_gpu_soft_reset()
5033 tmp = RREG32(SRBM_SOFT_RESET); in cik_gpu_soft_reset()
5037 tmp = RREG32(SRBM_SOFT_RESET); in cik_gpu_soft_reset()
5043 tmp = RREG32(SRBM_SOFT_RESET); in cik_gpu_soft_reset()
5064 save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE); in kv_save_regs_for_reset()
5065 save->gmcon_misc = RREG32(GMCON_MISC); in kv_save_regs_for_reset()
5066 save->gmcon_misc3 = RREG32(GMCON_MISC3); in kv_save_regs_for_reset()
5167 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_pci_config_reset()
5171 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_pci_config_reset()
5199 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) in cik_gpu_pci_config_reset()
5345 tmp = RREG32(MC_ARB_RAMCFG); in cik_mc_init()
5351 tmp = RREG32(MC_SHARED_CHMAP); in cik_mc_init()
5387 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in cik_mc_init()
5388 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in cik_mc_init()
5506 u32 tmp = RREG32(CHUB_CONTROL); in cik_pcie_gart_enable()
5556 rdev->vm_manager.saved_table_addr[i] = RREG32(reg); in cik_pcie_gart_disable()
5631 u64 tmp = RREG32(MC_VM_FB_OFFSET); in cik_vm_init()
5771 u32 tmp = RREG32(CP_INT_CNTL_RING0); in cik_enable_gui_idle_interrupt()
5784 tmp = RREG32(RLC_LB_CNTL); in cik_enable_lbpw()
5801 if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0) in cik_wait_for_rlc_serdes()
5811 if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) in cik_wait_for_rlc_serdes()
5821 tmp = RREG32(RLC_CNTL); in cik_update_rlc()
5830 orig = data = RREG32(RLC_CNTL); in cik_halt_rlc()
5839 if ((RREG32(RLC_GPM_STAT) & RLC_GPM_BUSY) == 0) in cik_halt_rlc()
5859 if ((RREG32(RLC_GPM_STAT) & mask) == mask) in cik_enter_rlc_safe_mode()
5865 if ((RREG32(RLC_GPR_REG2) & REQ) == 0) in cik_enter_rlc_safe_mode()
5930 tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc; in cik_rlc_resume()
6005 orig = data = RREG32(RLC_CGCG_CGLS_CTRL); in cik_enable_cgcg()
6024 RREG32(CB_CGTT_SCLK_CTRL); in cik_enable_cgcg()
6025 RREG32(CB_CGTT_SCLK_CTRL); in cik_enable_cgcg()
6026 RREG32(CB_CGTT_SCLK_CTRL); in cik_enable_cgcg()
6027 RREG32(CB_CGTT_SCLK_CTRL); in cik_enable_cgcg()
6044 orig = data = RREG32(CP_MEM_SLP_CNTL); in cik_enable_mgcg()
6051 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); in cik_enable_mgcg()
6068 orig = data = RREG32(CGTS_SM_CTRL_REG); in cik_enable_mgcg()
6083 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); in cik_enable_mgcg()
6088 data = RREG32(RLC_MEM_SLP_CNTL); in cik_enable_mgcg()
6094 data = RREG32(CP_MEM_SLP_CNTL); in cik_enable_mgcg()
6100 orig = data = RREG32(CGTS_SM_CTRL_REG); in cik_enable_mgcg()
6137 orig = data = RREG32(mc_cg_registers[i]); in cik_enable_mc_ls()
6154 orig = data = RREG32(mc_cg_registers[i]); in cik_enable_mc_mgcg()
6173 orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
6178 orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
6191 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
6196 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
6201 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
6206 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
6223 orig = data = RREG32(UVD_CGC_CTRL); in cik_enable_uvd_mgcg()
6232 orig = data = RREG32(UVD_CGC_CTRL); in cik_enable_uvd_mgcg()
6262 orig = data = RREG32(HDP_HOST_PATH_CNTL); in cik_enable_hdp_mgcg()
6278 orig = data = RREG32(HDP_MEM_POWER_LS); in cik_enable_hdp_ls()
6368 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_sck_slowdown_on_pu()
6382 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_sck_slowdown_on_pd()
6395 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_cp_pg()
6408 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gds_pg()
6511 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gfx_cgpg()
6516 orig = data = RREG32(RLC_AUTO_PG_CTRL); in cik_enable_gfx_cgpg()
6521 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gfx_cgpg()
6526 orig = data = RREG32(RLC_AUTO_PG_CTRL); in cik_enable_gfx_cgpg()
6531 data = RREG32(DB_RENDER_CONTROL); in cik_enable_gfx_cgpg()
6541 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG); in cik_get_cu_active_bitmap()
6542 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG); in cik_get_cu_active_bitmap()
6585 tmp = RREG32(RLC_MAX_PG_CU); in cik_init_ao_cu_mask()
6596 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gfx_static_mgpg()
6610 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gfx_dynamic_mgpg()
6643 orig = data = RREG32(RLC_PG_CNTL); in cik_init_gfx_cgpg()
6651 data = RREG32(CP_RB_WPTR_POLL_CNTL); in cik_init_gfx_cgpg()
6659 data = RREG32(RLC_PG_DELAY_2); in cik_init_gfx_cgpg()
6664 data = RREG32(RLC_AUTO_PG_CTRL); in cik_init_gfx_cgpg()
6825 u32 ih_cntl = RREG32(IH_CNTL); in cik_enable_interrupts()
6826 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_enable_interrupts()
6844 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_disable_interrupts()
6845 u32 ih_cntl = RREG32(IH_CNTL); in cik_disable_interrupts()
6870 tmp = RREG32(CP_INT_CNTL_RING0) & in cik_disable_interrupt_state()
6874 tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_disable_interrupt_state()
6876 tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_disable_interrupt_state()
6920 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
6922 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
6924 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
6926 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
6928 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
6930 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
6970 interrupt_cntl = RREG32(INTERRUPT_CNTL); in cik_irq_init()
7048 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set()
7052 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7053 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7054 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7055 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7056 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7057 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7059 dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_irq_set()
7060 dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_irq_set()
7062 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7063 cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7064 cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7065 cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7066 cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7067 cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7068 cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7069 cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7282 RREG32(SRBM_STATUS); in cik_irq_set()
7300 rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS); in cik_irq_ack()
7301 rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in cik_irq_ack()
7302 rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); in cik_irq_ack()
7303 rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); in cik_irq_ack()
7304 rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); in cik_irq_ack()
7305 rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); in cik_irq_ack()
7306 rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6); in cik_irq_ack()
7308 rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7310 rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7313 rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7315 rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7319 rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7321 rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7375 tmp = RREG32(DC_HPD1_INT_CONTROL); in cik_irq_ack()
7380 tmp = RREG32(DC_HPD2_INT_CONTROL); in cik_irq_ack()
7385 tmp = RREG32(DC_HPD3_INT_CONTROL); in cik_irq_ack()
7390 tmp = RREG32(DC_HPD4_INT_CONTROL); in cik_irq_ack()
7395 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
7400 tmp = RREG32(DC_HPD6_INT_CONTROL); in cik_irq_ack()
7405 tmp = RREG32(DC_HPD1_INT_CONTROL); in cik_irq_ack()
7410 tmp = RREG32(DC_HPD2_INT_CONTROL); in cik_irq_ack()
7415 tmp = RREG32(DC_HPD3_INT_CONTROL); in cik_irq_ack()
7420 tmp = RREG32(DC_HPD4_INT_CONTROL); in cik_irq_ack()
7425 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
7430 tmp = RREG32(DC_HPD6_INT_CONTROL); in cik_irq_ack()
7499 wptr = RREG32(IH_RB_WPTR); in cik_get_ih_wptr()
7510 tmp = RREG32(IH_RB_CNTL); in cik_get_ih_wptr()
7898 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); in cik_irq_process()
7907 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); in cik_irq_process()
7908 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS); in cik_irq_process()
7909 mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); in cik_irq_process()
8857 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce8_line_buffer_adjust()
8890 u32 tmp = RREG32(MC_SHARED_CHMAP); in cik_get_number_of_dram_channels()
9349 wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset); in dce8_program_watermarks()
9358 tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset); in dce8_program_watermarks()
9418 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | in cik_get_gpu_clock_counter()
9419 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); in cik_get_gpu_clock_counter()