Lines Matching defs:hqd_registers
4442 struct hqd_registers struct
4444 u32 cp_mqd_base_addr;
4445 u32 cp_mqd_base_addr_hi;
4446 u32 cp_hqd_active;
4447 u32 cp_hqd_vmid;
4448 u32 cp_hqd_persistent_state;
4449 u32 cp_hqd_pipe_priority;
4450 u32 cp_hqd_queue_priority;
4451 u32 cp_hqd_quantum;
4452 u32 cp_hqd_pq_base;
4453 u32 cp_hqd_pq_base_hi;
4454 u32 cp_hqd_pq_rptr;
4455 u32 cp_hqd_pq_rptr_report_addr;
4456 u32 cp_hqd_pq_rptr_report_addr_hi;
4457 u32 cp_hqd_pq_wptr_poll_addr;
4458 u32 cp_hqd_pq_wptr_poll_addr_hi;
4459 u32 cp_hqd_pq_doorbell_control;
4460 u32 cp_hqd_pq_wptr;
4461 u32 cp_hqd_pq_control;
4462 u32 cp_hqd_ib_base_addr;
4463 u32 cp_hqd_ib_base_addr_hi;
4464 u32 cp_hqd_ib_rptr;
4465 u32 cp_hqd_ib_control;
4466 u32 cp_hqd_iq_timer;
4467 u32 cp_hqd_iq_rptr;
4468 u32 cp_hqd_dequeue_request;
4469 u32 cp_hqd_dma_offload;
4470 u32 cp_hqd_sema_cmd;
4471 u32 cp_hqd_msg_type;
4472 u32 cp_hqd_atomic0_preop_lo;
4473 u32 cp_hqd_atomic0_preop_hi;
4474 u32 cp_hqd_atomic1_preop_lo;
4475 u32 cp_hqd_atomic1_preop_hi;
4476 u32 cp_hqd_hq_scheduler0;
4477 u32 cp_hqd_hq_scheduler1;
4478 u32 cp_mqd_control;