Lines Matching +full:sw +full:- +full:mode
2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
227 …USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change …
228 …USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the …
244 …USHORT ASIC_Init; //Function Table, used by various SW components,lat…
246 …USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW comp…
249 …USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW comp…
250 …USHORT EnableCRTCMemReq; //Function Table,directly used by various SW compon…
251 …USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,cal…
252 …USHORT DVOEncoderControl; //Function Table,directly used by various SW compon…
254 …USHORT SetEngineClock; //Function Table,directly used by various SW compon…
255 …USHORT SetMemoryClock; //Function Table,directly used by various SW compon…
256 …USHORT SetPixelClock; //Function Table,directly used by various SW compon…
257 …USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW comp…
258 …USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW comp…
259 …USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW comp…
261 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes.
262 …USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW comp…
265 …USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW compon…
266 …USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW componen…
267 …USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW compon…
268 …USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW compon…
269 …USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW compon…
270 …USHORT DVOOutputControl; //Atomic Table, directly used by various SW compon…
273 …USHORT TVEncoderControl; //Function Table,directly used by various SW compon…
278 …USHORT BlankCRTC; //Atomic Table, directly used by various SW compon…
279 …USHORT EnableCRTC; //Atomic Table, directly used by various SW compon…
280 …USHORT GetPixelClock; //Atomic Table, directly used by various SW compon…
281 …USHORT EnableVGA_Render; //Function Table,directly used by various SW compon…
283 …USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW compon…
284 …USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,late…
286 …USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW compon…
291 …USHORT GetMemoryClock; //Atomic Table, directly used by various SW compon…
292 …USHORT GetEngineClock; //Atomic Table, directly used by various SW compon…
293 …USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW compon…
294 …USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW compon…
295 …USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW compon…
299 …USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW comp…
300 …USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW comp…
301 …USHORT SpeedFanControl; //Function Table,indirectly used by various SW comp…
302 …USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW compon…
303 …USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW comp…
304 …USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW comp…
305 …USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW comp…
307 …USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW comp…
309 …USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW compon…
310 …USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW compon…
311 … //Function Table,directly and/or indirectly used by various SW components,latest ve…
312 …USHORT DAC1OutputControl; //Atomic Table, directly used by various SW compon…
313 …USHORT DAC2OutputControl; //Atomic Table, directly used by various SW compon…
315 …USHORT ClockSource; //Atomic Table, indirectly used by various SW comp…
316 …USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW comp…
317 …USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW comp…
318 …USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW componen…
319 …USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW componen…
320 …USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW componen…
321 …USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW component…
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …R ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
730 #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this …
815 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
861 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
868 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
920 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
921 …UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to prev…
954 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
959 // [1]=0: InCoherent mode
960 // =1: Coherent Mode
1034 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1038 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1082 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1099 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1103 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1121 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1174 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1178 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1195 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1199 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1216 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version
1273 …USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= p…
1276 UCHAR ucLaneNum; // indicate lane number 1-8
1278 UCHAR ucDigMode; // indicate DIG mode
1369 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
1513 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1626 …// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the sour…
1648 UCHAR ucEncoderMode; // Encoder mode:
1653 // =0: XTLAIN( default mode )
1654 // =1: other external clock source, which is pre-defined
1696 UCHAR ucEncoderMode; // Encoder mode:
1701 // =0: XTLAIN( default mode )
1702 …// =1: other external clock source, which is pre-defined …
1761 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
1783 …UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other …
1784 …UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other …
1830 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
1938 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1939 // Bit[1]: 1-Ext. 0-Int.
1963 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1964 // Bit[1]: 1-Ext. 0-Int.
2149 // bit1=0: non-coherent mode
2150 // =1: coherent mode
2224 …AR ucVoltageMode; // Not used, maybe use for state machine for differen power mode
2353 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
2355 …USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was…
2357 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1
2359 …USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will…
2360 …USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will…
2361 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
2363 …USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will…
2364 …USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new …
2367 …USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, use…
2368 …USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
2370 …USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, onl…
2371 USHORT Object_Header; // Shared by various SW components,latest version 1.1
2379 USHORT IntegratedSystemInfo; // Shared by various SW components
2380 …SIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2381 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
2382 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
2567 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2604 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2642 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2681 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2685 … usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock …
2724 … usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock …
2764 //Bit[4]==1: P/2 mode, ==0: P/1 mode
2781 … For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
2782 … IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
2784 …emoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
2812 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data…
2813 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW c…
2815 SW components can access the IGP system infor structure in the same way as before
2857 … // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
2862 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
2863 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
2864 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
2867 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
2868 … at AMD overdrived state or user customized mode. In this case, driver will just stick to this bo…
2879 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using l…
2880 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
2886 …ord is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEV…
2888 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
2889 …[7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are suppor…
2892 …[3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lan…
2893 …[7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station…
2896 …one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connect…
2898 [15:8] - Lane configuration attribute;
2899 [23:16]- Connector type, possible value:
2905 [31:24]- Reserved
2913 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offs…
2921 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
2922 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
2923 …GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_US…
2924 …PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE…
2925 …GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYST…
2927 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
2955 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
3153 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3154 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3155 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3156 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3157 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3158 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3159 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3160 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3161 // Bit 8 = 0 - no CV support= 1- CV is supported
3162 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3163 // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported
3164 // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported
3172 // [7:0] - I2C LINE Associate ID
3173 // = 0 - no I2C
3174 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3175 // = 0, [6:0]=SW assisted I2C ID
3176 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3178 // = 3-7 Reserved for future I2C engines
3179 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3284 // usModeMiscInfo-
3296 //usRefreshRate-
3469 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3478 // 0 0 0 - Color bit depth is undefined
3479 // 0 0 1 - 6 Bits per Primary Color
3480 // 0 1 0 - 8 Bits per Primary Color
3481 // 0 1 1 - 10 Bits per Primary Color
3482 // 1 0 0 - 12 Bits per Primary Color
3483 // 1 0 1 - 14 Bits per Primary Color
3484 // 1 1 0 - 16 Bits per Primary Color
3485 // 1 1 1 - Reserved
3523 // Bit7-3: Reserved
3542 …RT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode.
3561 // 0 0 0 - Color bit depth is undefined
3562 // 0 0 1 - 6 Bits per Primary Color
3563 // 0 1 0 - 8 Bits per Primary Color
3564 // 0 1 1 - 10 Bits per Primary Color
3565 // 1 0 0 - 12 Bits per Primary Color
3566 // 1 0 1 - 14 Bits per Primary Color
3567 // 1 1 0 - 16 Bits per Primary Color
3568 // 1 1 1 - Reserved
3578 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3585 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
3586 …_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW in…
3587 #define eDP_TO_LVDS_RT_ID 0x02 // RT tanslator which require AMD SW init
3738 // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down …
3741 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
3754 …(ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
3812 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)…
3835 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
3839 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
3841 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
3885 //ucGPIO_ID pre-define id for multiple usage
3945 //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
3946 …//bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
3947 …//bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
3967 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
3984 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4288 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4341 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4347 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4480 …UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /Vo…
4568 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase
4573 #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_V…
4574 …I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OB…
4575 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GP…
4576 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SV…
4578 …OST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4579 …AKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4580 …AKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4597 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
4612 …ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHA…
4613 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode
4623 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12
4634 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2
4864 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
4880 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
4881 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
4882 bit[3]=0: Enable HW AUX mode detection logic
4883 =1: Disable HW AUX mode dettion logic
4886 …FreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
4889 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
4890 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
4892 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
4895 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
4898 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
4909 Bit[1]=0: DDR-DLL shut-down feature disabled.
4910 1: DDR-DLL shut-down feature enabled.
4911 Bit[2]=0: DDR-PLL Power down feature disabled.
4912 … 1: DDR-PLL Power down feature enabled.
4931 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
4932 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
4944 … [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel …
4946 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
5079 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
5100 …S fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is con…
5101 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
5102 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
5103 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
5104 =1: DP mode use single PLL mode
5105 bit[3]=0: Enable AUX HW mode detection logic
5106 =1: Disable AUX HW mode detection logic
5110 …FreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
5113 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5114 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5116 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5119 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5122 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5133 Bit[1]=0: DDR-DLL shut-down feature disabled.
5134 1: DDR-DLL shut-down feature enabled.
5135 Bit[2]=0: DDR-PLL Power down feature disabled.
5136 … 1: DDR-PLL Power down feature enabled.
5157 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
5158 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5170 … [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel …
5172 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
5179 …default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5182 …fault which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5186 …t delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5190 …fault which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5280 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
5303 …S fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is con…
5306 bit[3]=0: Enable AUX HW mode detection logic
5307 =1: Disable AUX HW mode detection logic
5311 …FreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
5314 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5315 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5317 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5320 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5323 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5333 Bit[1]=0: DDR-DLL shut-down feature disabled.
5334 1: DDR-DLL shut-down feature enabled.
5335 Bit[2]=0: DDR-PLL Power down feature disabled.
5336 1: DDR-PLL Power down feature enabled.
5357 … NCLK speed while memory runs in self-refresh state, used to calculate self-re…
5375 … [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel …
5377 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
5385 …default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5389 …fault which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5393 …t delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5397 …fault which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5416 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
5417 ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State
5418 usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
5419 usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded
5439 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
5442 …s; //Indicates how many bytes SW needs to write to th…
5447 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C pro…
5450 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap.
5480 //Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a cloc…
5688 …S_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode
5981 …char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<cha…
5983 …ADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevisio…
5984 …DER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevisi…
5986 …ieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeo…
5988 …SION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevisio…
5989 …ION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevisi…
6207 UCHAR ucVMode_Num; //Video mode number
6208 UCHAR ucTV_Mode_Num; //Internal TV mode number
6369 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
6407 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
6408 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
6425 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
6434 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
6435 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
6445 USHORT usMRS; // mode register
6449 USHORT usEMRS; // extended mode register
6480 USHORT usMRS; // mode register
6481 USHORT usEMRS; // extended mode register
6513 USHORT usMRS; // mode register
6514 USHORT usEMRS; // extended mode register
6557 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
6564 … ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
6582 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
6603 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6605 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6608 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
6613 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6645 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6647 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6650 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
6655 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6664 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6676 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6678 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6681 …HAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
6686 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6695 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6714 … // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
6716 …Size; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6725 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6816 /****************************SW I2C CNTL DEFINITIONS**********************/
6905 USHORT ModeAttributes; // dw ? ; mode attributes
6912 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
6937 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes
6941 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
6942 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
6956 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
7299 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
7300 …gListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's …
7301 …ttingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting fo…
7308 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
7309 …gListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's …
7310 …ttingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting fo…
7450 // [7:4] - connector type
7451 // = 1 - VGA connector
7452 // = 2 - DVI-I
7453 // = 3 - DVI-D
7454 // = 4 - DVI-A
7455 // = 5 - SVIDEO
7456 // = 6 - COMPOSITE
7457 // = 7 - LVDS
7458 // = 8 - DIGITAL LINK
7459 // = 9 - SCART
7460 // = 0xA - HDMI_type A
7461 // = 0xB - HDMI_type B
7462 // = 0xE - Special case1 (DVI+DIN)
7464 // [3:0] - DAC Associated
7465 // = 0 - no DAC
7466 // = 1 - DACA
7467 // = 2 - DACB
7468 // = 3 - External DAC
7533 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
7627 … bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program
7643 …SCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-…
7651 …SCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode
7653 …ETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-Hi…
7663 …IDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will…
7664 …//If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video pla…
7768 // Following definitions are for compatibility issue in different SW components.