120 #define ST7701_DSI(st7701, seq...)				\  macro
130 	ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00);  in st7701_init_sequence()
135 	ST7701_DSI(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);  in st7701_init_sequence()
140 	ST7701_DSI(st7701, DSI_CMD2BKX_SEL,  in st7701_init_sequence()
142 	ST7701_DSI(st7701, DSI_CMD2_BK0_PVGAMCTRL, 0x00, 0x0E, 0x15, 0x0F,  in st7701_init_sequence()
145 	ST7701_DSI(st7701, DSI_CMD2_BK0_NVGAMCTRL, 0x00, 0x0E, 0x95, 0x0F,  in st7701_init_sequence()
148 	ST7701_DSI(st7701, DSI_CMD2_BK0_LNESET,  in st7701_init_sequence()
150 	ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL,  in st7701_init_sequence()
153 	ST7701_DSI(st7701, DSI_CMD2_BK0_INVSEL,  in st7701_init_sequence()
157 	ST7701_DSI(st7701, DSI_CMD2BKX_SEL,  in st7701_init_sequence()
159 	ST7701_DSI(st7701, DSI_CMD2_BK1_VRHS, DSI_CMD2_BK1_VRHA_SET);  in st7701_init_sequence()
160 	ST7701_DSI(st7701, DSI_CMD2_BK1_VCOM, DSI_CMD2_BK1_VCOM_SET);  in st7701_init_sequence()
161 	ST7701_DSI(st7701, DSI_CMD2_BK1_VGHSS, DSI_CMD2_BK1_VGHSS_SET);  in st7701_init_sequence()
162 	ST7701_DSI(st7701, DSI_CMD2_BK1_TESTCMD, DSI_CMD2_BK1_TESTCMD_VAL);  in st7701_init_sequence()
163 	ST7701_DSI(st7701, DSI_CMD2_BK1_VGLS, DSI_CMD2_BK1_VGLS_SET);  in st7701_init_sequence()
164 	ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR1, DSI_CMD2_BK1_PWCTLR1_SET);  in st7701_init_sequence()
165 	ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR2, DSI_CMD2_BK1_PWCTLR2_SET);  in st7701_init_sequence()
166 	ST7701_DSI(st7701, DSI_CMD2_BK1_SPD1, DSI_CMD2_BK1_SPD1_SET);  in st7701_init_sequence()
167 	ST7701_DSI(st7701, DSI_CMD2_BK1_SPD2, DSI_CMD2_BK1_SPD2_SET);  in st7701_init_sequence()
168 	ST7701_DSI(st7701, DSI_CMD2_BK1_MIPISET1, DSI_CMD2_BK1_MIPISET1_SET);  in st7701_init_sequence()
174 	ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);  in st7701_init_sequence()
175 	ST7701_DSI(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E,  in st7701_init_sequence()
177 	ST7701_DSI(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66,  in st7701_init_sequence()
179 	ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);  in st7701_init_sequence()
180 	ST7701_DSI(st7701, 0xE4, 0x44, 0x44);  in st7701_init_sequence()
181 	ST7701_DSI(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C,  in st7701_init_sequence()
183 	ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);  in st7701_init_sequence()
184 	ST7701_DSI(st7701, 0xE7, 0x44, 0x44);  in st7701_init_sequence()
185 	ST7701_DSI(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C,  in st7701_init_sequence()
187 	ST7701_DSI(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00);  in st7701_init_sequence()
188 	ST7701_DSI(st7701, 0xEC, 0x00, 0x00);  in st7701_init_sequence()
189 	ST7701_DSI(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF,  in st7701_init_sequence()
193 	ST7701_DSI(st7701, DSI_CMD2BKX_SEL,  in st7701_init_sequence()
222 	ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00);  in st7701_enable()
231 	ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00);  in st7701_disable()
240 	ST7701_DSI(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00);  in st7701_unprepare()