406 	struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);  in nv50_outp_atomic_check()  local
415 		asyh->or.bpc = connector->display_info.bpc;  in nv50_outp_atomic_check()
474 	struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);  in nv50_dac_enable()  local
492 	core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh);  in nv50_dac_enable()
493 	asyh->or.depth = 0;  in nv50_dac_enable()
1011 	struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);  in nv50_msto_atomic_check()  local
1031 		asyh->or.bpc = connector->display_info.bpc;  in nv50_msto_atomic_check()
1032 		asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,  in nv50_msto_atomic_check()
1037 					      asyh->dp.pbn, 0);  in nv50_msto_atomic_check()
1041 	asyh->dp.tu = slots;  in nv50_msto_atomic_check()
1597 		struct nv50_head_atom *asyh, u8 proto, u8 depth)  in nv50_sor_update()  argument
1602 	if (!asyh) {  in nv50_sor_update()
1609 		asyh->or.depth = depth;  in nv50_sor_update()
1612 	core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);  in nv50_sor_update()
1652 	struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);  in nv50_sor_enable()  local
1653 	struct drm_display_mode *mode = &asyh->state.adjusted_mode;  in nv50_sor_enable()
1726 			if (asyh->or.bpc == 8)  in nv50_sor_enable()
1733 		depth = nv50_dp_bpc_to_depth(asyh->or.bpc);  in nv50_sor_enable()
1747 	nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);  in nv50_sor_enable()
1891 	struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);  in nv50_pior_enable()  local
1905 	switch (asyh->or.bpc) {  in nv50_pior_enable()
1906 	case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;  in nv50_pior_enable()
1907 	case  8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;  in nv50_pior_enable()
1908 	case  6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;  in nv50_pior_enable()
1909 	default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;  in nv50_pior_enable()
1922 	core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh);  in nv50_pior_enable()
2078 		struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);  in nv50_disp_atomic_commit_tail()  local
2082 			  asyh->clr.mask, asyh->set.mask);  in nv50_disp_atomic_commit_tail()
2089 		if (asyh->clr.mask) {  in nv50_disp_atomic_commit_tail()
2090 			nv50_head_flush_clr(head, asyh, atom->flush_disable);  in nv50_disp_atomic_commit_tail()
2169 		struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);  in nv50_disp_atomic_commit_tail()  local
2173 			  asyh->set.mask, asyh->clr.mask);  in nv50_disp_atomic_commit_tail()
2175 		if (asyh->set.mask) {  in nv50_disp_atomic_commit_tail()
2176 			nv50_head_flush_set(head, asyh);  in nv50_disp_atomic_commit_tail()
2220 		struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);  in nv50_disp_atomic_commit_tail()  local
2224 			  asyh->set.mask, asyh->clr.mask);  in nv50_disp_atomic_commit_tail()
2226 		if (asyh->set.mask) {  in nv50_disp_atomic_commit_tail()
2227 			nv50_head_flush_set_wndw(head, asyh);  in nv50_disp_atomic_commit_tail()
2455 	struct nv50_head_atom *asyh;  in nv50_disp_atomic_check()  local
2466 			asyh = nv50_head_atom(new_crtc_state);  in nv50_disp_atomic_check()
2467 			core->func->head->static_wndw_map(head, asyh);  in nv50_disp_atomic_check()