396 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];  in nv_save_state_ramdac()  local
400 		regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);  in nv_save_state_ramdac()
402 	nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, &regp->pllvals);  in nv_save_state_ramdac()
407 		regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);  in nv_save_state_ramdac()
409 	regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);  in nv_save_state_ramdac()
412 		regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);  in nv_save_state_ramdac()
414 		regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);  in nv_save_state_ramdac()
416 	regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);  in nv_save_state_ramdac()
417 	regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL);  in nv_save_state_ramdac()
418 	regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW);  in nv_save_state_ramdac()
419 	regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY);  in nv_save_state_ramdac()
420 	regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL);  in nv_save_state_ramdac()
421 	regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW);  in nv_save_state_ramdac()
422 	regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY);  in nv_save_state_ramdac()
423 	regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2);  in nv_save_state_ramdac()
427 		regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg);  in nv_save_state_ramdac()
428 		regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20);  in nv_save_state_ramdac()
432 		regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER);  in nv_save_state_ramdac()
434 			regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4);  in nv_save_state_ramdac()
435 			regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4);  in nv_save_state_ramdac()
439 	regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);  in nv_save_state_ramdac()
440 	regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0);  in nv_save_state_ramdac()
444 		NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 &  in nv_save_state_ramdac()
447 	regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1);  in nv_save_state_ramdac()
448 	regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2);  in nv_save_state_ramdac()
450 	regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR);  in nv_save_state_ramdac()
453 		regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);  in nv_save_state_ramdac()
456 		regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);  in nv_save_state_ramdac()
457 		regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);  in nv_save_state_ramdac()
458 		regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);  in nv_save_state_ramdac()
461 			regp->ctv_regs[i] = NVReadRAMDAC(dev, head,  in nv_save_state_ramdac()
472 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];  in nv_load_state_ramdac()  local
477 		NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);  in nv_load_state_ramdac()
479 	clk->pll_prog(clk, pllreg, &regp->pllvals);  in nv_load_state_ramdac()
484 		NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither);  in nv_load_state_ramdac()
486 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);  in nv_load_state_ramdac()
489 		NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630);  in nv_load_state_ramdac()
491 		NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634);  in nv_load_state_ramdac()
493 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup);  in nv_load_state_ramdac()
494 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal);  in nv_load_state_ramdac()
495 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew);  in nv_load_state_ramdac()
496 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay);  in nv_load_state_ramdac()
497 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal);  in nv_load_state_ramdac()
498 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew);  in nv_load_state_ramdac()
499 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay);  in nv_load_state_ramdac()
500 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2);  in nv_load_state_ramdac()
505 		NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]);  in nv_load_state_ramdac()
506 		NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]);  in nv_load_state_ramdac()
510 		NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither);  in nv_load_state_ramdac()
512 			NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]);  in nv_load_state_ramdac()
513 			NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]);  in nv_load_state_ramdac()
517 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control);  in nv_load_state_ramdac()
518 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0);  in nv_load_state_ramdac()
519 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1);  in nv_load_state_ramdac()
520 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2);  in nv_load_state_ramdac()
522 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color);  in nv_load_state_ramdac()
525 		NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);  in nv_load_state_ramdac()
528 		NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);  in nv_load_state_ramdac()
529 		NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);  in nv_load_state_ramdac()
530 		NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);  in nv_load_state_ramdac()
534 				      NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]);  in nv_load_state_ramdac()
542 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];  in nv_save_state_vga()  local
545 	regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ);  in nv_save_state_vga()
548 		rd_cio_state(dev, head, regp, i);  in nv_save_state_vga()
552 		regp->Attribute[i] = NVReadVgaAttr(dev, head, i);  in nv_save_state_vga()
556 		regp->Graphics[i] = NVReadVgaGr(dev, head, i);  in nv_save_state_vga()
559 		regp->Sequencer[i] = NVReadVgaSeq(dev, head, i);  in nv_save_state_vga()
566 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];  in nv_load_state_vga()  local
569 	NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);  in nv_load_state_vga()
572 		NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]);  in nv_load_state_vga()
576 		wr_cio_state(dev, head, regp, i);  in nv_load_state_vga()
580 		NVWriteVgaGr(dev, head, i, regp->Graphics[i]);  in nv_load_state_vga()
584 		NVWriteVgaAttr(dev, head, i, regp->Attribute[i]);  in nv_load_state_vga()
593 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];  in nv_save_state_ext()  local
596 	rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);  in nv_save_state_ext()
597 	rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);  in nv_save_state_ext()
598 	rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);  in nv_save_state_ext()
599 	rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);  in nv_save_state_ext()
600 	rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);  in nv_save_state_ext()
601 	rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);  in nv_save_state_ext()
602 	rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);  in nv_save_state_ext()
604 	rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);  in nv_save_state_ext()
605 	rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);  in nv_save_state_ext()
606 	rd_cio_state(dev, head, regp, NV_CIO_CRE_21);  in nv_save_state_ext()
609 		rd_cio_state(dev, head, regp, NV_CIO_CRE_47);  in nv_save_state_ext()
612 		rd_cio_state(dev, head, regp, 0x9f);  in nv_save_state_ext()
614 	rd_cio_state(dev, head, regp, NV_CIO_CRE_49);  in nv_save_state_ext()
615 	rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);  in nv_save_state_ext()
616 	rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);  in nv_save_state_ext()
617 	rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);  in nv_save_state_ext()
618 	rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);  in nv_save_state_ext()
621 		regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);  in nv_save_state_ext()
622 		regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);  in nv_save_state_ext()
625 			regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);  in nv_save_state_ext()
628 			regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);  in nv_save_state_ext()
631 			regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL);  in nv_save_state_ext()
632 		regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG);  in nv_save_state_ext()
635 	regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG);  in nv_save_state_ext()
637 	rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);  in nv_save_state_ext()
638 	rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);  in nv_save_state_ext()
640 		rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);  in nv_save_state_ext()
641 		rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);  in nv_save_state_ext()
642 		rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);  in nv_save_state_ext()
643 		rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);  in nv_save_state_ext()
647 		rd_cio_state(dev, head, regp, NV_CIO_CRE_42);  in nv_save_state_ext()
648 		rd_cio_state(dev, head, regp, NV_CIO_CRE_53);  in nv_save_state_ext()
649 		rd_cio_state(dev, head, regp, NV_CIO_CRE_54);  in nv_save_state_ext()
652 			regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i);  in nv_save_state_ext()
653 		rd_cio_state(dev, head, regp, NV_CIO_CRE_59);  in nv_save_state_ext()
654 		rd_cio_state(dev, head, regp, NV_CIO_CRE_5B);  in nv_save_state_ext()
656 		rd_cio_state(dev, head, regp, NV_CIO_CRE_85);  in nv_save_state_ext()
657 		rd_cio_state(dev, head, regp, NV_CIO_CRE_86);  in nv_save_state_ext()
660 	regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START);  in nv_save_state_ext()
669 	struct nv04_crtc_reg *regp = &state->crtc_reg[head];  in nv_load_state_ext()  local
679 			NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);  in nv_load_state_ext()
691 		NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);  in nv_load_state_ext()
692 		NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);  in nv_load_state_ext()
693 		NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);  in nv_load_state_ext()
696 			NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);  in nv_load_state_ext()
699 			NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);  in nv_load_state_ext()
702 			if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC)  in nv_load_state_ext()
709 	NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg);  in nv_load_state_ext()
711 	wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);  in nv_load_state_ext()
712 	wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);  in nv_load_state_ext()
713 	wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);  in nv_load_state_ext()
714 	wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);  in nv_load_state_ext()
715 	wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);  in nv_load_state_ext()
716 	wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);  in nv_load_state_ext()
717 	wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);  in nv_load_state_ext()
718 	wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);  in nv_load_state_ext()
719 	wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);  in nv_load_state_ext()
722 		wr_cio_state(dev, head, regp, NV_CIO_CRE_47);  in nv_load_state_ext()
725 		wr_cio_state(dev, head, regp, 0x9f);  in nv_load_state_ext()
727 	wr_cio_state(dev, head, regp, NV_CIO_CRE_49);  in nv_load_state_ext()
728 	wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);  in nv_load_state_ext()
729 	wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);  in nv_load_state_ext()
730 	wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);  in nv_load_state_ext()
733 	wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);  in nv_load_state_ext()
735 	wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);  in nv_load_state_ext()
736 	wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);  in nv_load_state_ext()
738 		wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);  in nv_load_state_ext()
739 		wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);  in nv_load_state_ext()
740 		wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);  in nv_load_state_ext()
741 		wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);  in nv_load_state_ext()
758 		wr_cio_state(dev, head, regp, NV_CIO_CRE_42);  in nv_load_state_ext()
759 		wr_cio_state(dev, head, regp, NV_CIO_CRE_53);  in nv_load_state_ext()
760 		wr_cio_state(dev, head, regp, NV_CIO_CRE_54);  in nv_load_state_ext()
763 			NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]);  in nv_load_state_ext()
764 		wr_cio_state(dev, head, regp, NV_CIO_CRE_59);  in nv_load_state_ext()
765 		wr_cio_state(dev, head, regp, NV_CIO_CRE_5B);  in nv_load_state_ext()
767 		wr_cio_state(dev, head, regp, NV_CIO_CRE_85);  in nv_load_state_ext()
768 		wr_cio_state(dev, head, regp, NV_CIO_CRE_86);  in nv_load_state_ext()
771 	NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start);  in nv_load_state_ext()