Lines Matching refs:wm
455 mutex_lock(&dev_priv->wm.wm_mutex); in intel_set_memory_cxsr()
458 dev_priv->wm.vlv.cxsr = enable; in intel_set_memory_cxsr()
460 dev_priv->wm.g4x.cxsr = enable; in intel_set_memory_cxsr()
461 mutex_unlock(&dev_priv->wm.wm_mutex); in intel_set_memory_cxsr()
489 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_get_fifo_size()
769 const struct intel_watermark_params *wm, in intel_calculate_wm() argument
783 entries = DIV_ROUND_UP(entries, wm->cacheline_size) + in intel_calculate_wm()
784 wm->guard_size; in intel_calculate_wm()
791 if (wm_size > wm->max_wm) in intel_calculate_wm()
792 wm_size = wm->max_wm; in intel_calculate_wm()
794 wm_size = wm->default_wm; in intel_calculate_wm()
821 return dev_priv->wm.max_level + 1; in intel_wm_num_levels()
887 unsigned int wm; in pnv_update_wm() local
910 wm = intel_calculate_wm(clock, &pnv_display_wm, in pnv_update_wm()
915 reg |= FW_WM(wm, SR); in pnv_update_wm()
920 wm = intel_calculate_wm(clock, &pnv_cursor_wm, in pnv_update_wm()
925 reg |= FW_WM(wm, CURSOR_SR); in pnv_update_wm()
929 wm = intel_calculate_wm(clock, &pnv_display_hplloff_wm, in pnv_update_wm()
934 reg |= FW_WM(wm, HPLL_SR); in pnv_update_wm()
938 wm = intel_calculate_wm(clock, &pnv_cursor_hplloff_wm, in pnv_update_wm()
943 reg |= FW_WM(wm, HPLL_CURSOR); in pnv_update_wm()
971 const struct g4x_wm_values *wm) in g4x_write_wm_values() argument
976 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm); in g4x_write_wm_values()
979 FW_WM(wm->sr.plane, SR) | in g4x_write_wm_values()
980 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in g4x_write_wm_values()
981 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in g4x_write_wm_values()
982 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in g4x_write_wm_values()
984 (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) | in g4x_write_wm_values()
985 FW_WM(wm->sr.fbc, FBC_SR) | in g4x_write_wm_values()
986 FW_WM(wm->hpll.fbc, FBC_HPLL_SR) | in g4x_write_wm_values()
987 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | in g4x_write_wm_values()
988 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in g4x_write_wm_values()
989 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in g4x_write_wm_values()
991 (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) | in g4x_write_wm_values()
992 FW_WM(wm->sr.cursor, CURSOR_SR) | in g4x_write_wm_values()
993 FW_WM(wm->hpll.cursor, HPLL_CURSOR) | in g4x_write_wm_values()
994 FW_WM(wm->hpll.plane, HPLL_SR)); in g4x_write_wm_values()
1003 const struct vlv_wm_values *wm) in vlv_write_wm_values() argument
1008 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm); in vlv_write_wm_values()
1011 (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) | in vlv_write_wm_values()
1012 (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) | in vlv_write_wm_values()
1013 (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) | in vlv_write_wm_values()
1014 (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT)); in vlv_write_wm_values()
1029 FW_WM(wm->sr.plane, SR) | in vlv_write_wm_values()
1030 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in vlv_write_wm_values()
1031 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in vlv_write_wm_values()
1032 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in vlv_write_wm_values()
1034 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | in vlv_write_wm_values()
1035 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in vlv_write_wm_values()
1036 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in vlv_write_wm_values()
1038 FW_WM(wm->sr.cursor, CURSOR_SR)); in vlv_write_wm_values()
1042 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | in vlv_write_wm_values()
1043 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); in vlv_write_wm_values()
1045 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) | in vlv_write_wm_values()
1046 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE)); in vlv_write_wm_values()
1048 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) | in vlv_write_wm_values()
1049 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC)); in vlv_write_wm_values()
1051 FW_WM(wm->sr.plane >> 9, SR_HI) | in vlv_write_wm_values()
1052 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) | in vlv_write_wm_values()
1053 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) | in vlv_write_wm_values()
1054 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) | in vlv_write_wm_values()
1055 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
1056 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
1057 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | in vlv_write_wm_values()
1058 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
1059 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
1060 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); in vlv_write_wm_values()
1063 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | in vlv_write_wm_values()
1064 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); in vlv_write_wm_values()
1066 FW_WM(wm->sr.plane >> 9, SR_HI) | in vlv_write_wm_values()
1067 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
1068 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
1069 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | in vlv_write_wm_values()
1070 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
1071 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
1072 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); in vlv_write_wm_values()
1083 dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5; in g4x_setup_wm_latency()
1084 dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12; in g4x_setup_wm_latency()
1085 dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35; in g4x_setup_wm_latency()
1087 dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL; in g4x_setup_wm_latency()
1140 unsigned int latency = dev_priv->wm.pri_latency[level] * 10; in g4x_compute_wm()
1141 unsigned int clock, htotal, cpp, width, wm; in g4x_compute_wm() local
1172 wm = intel_wm_method2(clock, htotal, width, cpp, latency); in g4x_compute_wm()
1175 wm = intel_wm_method1(clock, cpp, latency); in g4x_compute_wm()
1182 wm = min(small, large); in g4x_compute_wm()
1185 wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level), in g4x_compute_wm()
1188 wm = DIV_ROUND_UP(wm, 64) + 2; in g4x_compute_wm()
1190 return min_t(unsigned int, wm, USHRT_MAX); in g4x_compute_wm()
1200 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_plane_wm_set()
1219 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_fbc_wm_set()
1250 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_plane_wm_compute()
1251 int wm, max_wm; in g4x_raw_plane_wm_compute() local
1253 wm = g4x_compute_wm(crtc_state, plane_state, level); in g4x_raw_plane_wm_compute()
1256 if (wm > max_wm) in g4x_raw_plane_wm_compute()
1259 dirty |= raw->plane[plane_id] != wm; in g4x_raw_plane_wm_compute()
1260 raw->plane[plane_id] = wm; in g4x_raw_plane_wm_compute()
1266 wm = ilk_compute_fbc_wm(crtc_state, plane_state, in g4x_raw_plane_wm_compute()
1274 if (wm > max_wm) in g4x_raw_plane_wm_compute()
1275 wm = USHRT_MAX; in g4x_raw_plane_wm_compute()
1277 dirty |= raw->fbc != wm; in g4x_raw_plane_wm_compute()
1278 raw->fbc = wm; in g4x_raw_plane_wm_compute()
1292 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id], in g4x_raw_plane_wm_compute()
1293 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id], in g4x_raw_plane_wm_compute()
1294 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]); in g4x_raw_plane_wm_compute()
1299 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc, in g4x_raw_plane_wm_compute()
1300 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc); in g4x_raw_plane_wm_compute()
1309 const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_plane_wm_is_valid()
1319 if (level > dev_priv->wm.max_level) in g4x_raw_crtc_wm_is_valid()
1335 wm_state->wm.plane[plane_id] = USHRT_MAX; in g4x_invalidate_wms()
1375 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; in g4x_compute_pipe_wm()
1404 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1406 wm_state->wm.plane[plane_id] = raw->plane[plane_id]; in g4x_compute_pipe_wm()
1412 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1423 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1455 struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate; in g4x_compute_intermediate_wm()
1456 const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal; in g4x_compute_intermediate_wm()
1461 const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal; in g4x_compute_intermediate_wm()
1479 intermediate->wm.plane[plane_id] = in g4x_compute_intermediate_wm()
1480 max(optimal->wm.plane[plane_id], in g4x_compute_intermediate_wm()
1481 active->wm.plane[plane_id]); in g4x_compute_intermediate_wm()
1483 drm_WARN_ON(&dev_priv->drm, intermediate->wm.plane[plane_id] > in g4x_compute_intermediate_wm()
1527 new_crtc_state->wm.need_postvbl_update = true; in g4x_compute_intermediate_wm()
1533 struct g4x_wm_values *wm) in g4x_merge_wm() argument
1538 wm->cxsr = true; in g4x_merge_wm()
1539 wm->hpll_en = true; in g4x_merge_wm()
1540 wm->fbc_en = true; in g4x_merge_wm()
1543 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; in g4x_merge_wm()
1549 wm->cxsr = false; in g4x_merge_wm()
1551 wm->hpll_en = false; in g4x_merge_wm()
1553 wm->fbc_en = false; in g4x_merge_wm()
1559 wm->cxsr = false; in g4x_merge_wm()
1560 wm->hpll_en = false; in g4x_merge_wm()
1561 wm->fbc_en = false; in g4x_merge_wm()
1565 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; in g4x_merge_wm()
1568 wm->pipe[pipe] = wm_state->wm; in g4x_merge_wm()
1569 if (crtc->active && wm->cxsr) in g4x_merge_wm()
1570 wm->sr = wm_state->sr; in g4x_merge_wm()
1571 if (crtc->active && wm->hpll_en) in g4x_merge_wm()
1572 wm->hpll = wm_state->hpll; in g4x_merge_wm()
1578 struct g4x_wm_values *old_wm = &dev_priv->wm.g4x; in g4x_program_watermarks()
1604 mutex_lock(&dev_priv->wm.wm_mutex); in g4x_initial_watermarks()
1605 crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate; in g4x_initial_watermarks()
1607 mutex_unlock(&dev_priv->wm.wm_mutex); in g4x_initial_watermarks()
1617 if (!crtc_state->wm.need_postvbl_update) in g4x_optimize_watermarks()
1620 mutex_lock(&dev_priv->wm.wm_mutex); in g4x_optimize_watermarks()
1621 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; in g4x_optimize_watermarks()
1623 mutex_unlock(&dev_priv->wm.wm_mutex); in g4x_optimize_watermarks()
1645 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; in vlv_setup_wm_latency()
1647 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; in vlv_setup_wm_latency()
1650 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; in vlv_setup_wm_latency()
1651 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; in vlv_setup_wm_latency()
1653 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; in vlv_setup_wm_latency()
1665 unsigned int clock, htotal, cpp, width, wm; in vlv_compute_wm_level() local
1667 if (dev_priv->wm.pri_latency[level] == 0) in vlv_compute_wm_level()
1685 wm = 63; in vlv_compute_wm_level()
1687 wm = vlv_wm_method2(clock, htotal, width, cpp, in vlv_compute_wm_level()
1688 dev_priv->wm.pri_latency[level] * 10); in vlv_compute_wm_level()
1691 return min_t(unsigned int, wm, USHRT_MAX); in vlv_compute_wm_level()
1705 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2]; in vlv_compute_fifo()
1706 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_compute_fifo()
1793 wm_state->wm[level].plane[plane_id] = USHRT_MAX; in vlv_invalidate_wms()
1800 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size) in vlv_invert_wm_value() argument
1802 if (wm > fifo_size) in vlv_invert_wm_value()
1805 return fifo_size - wm; in vlv_invert_wm_value()
1820 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_set()
1845 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_compute()
1846 int wm = vlv_compute_wm_level(crtc_state, plane_state, level); in vlv_raw_plane_wm_compute() local
1849 if (wm > max_wm) in vlv_raw_plane_wm_compute()
1852 dirty |= raw->plane[plane_id] != wm; in vlv_raw_plane_wm_compute()
1853 raw->plane[plane_id] = wm; in vlv_raw_plane_wm_compute()
1864 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id], in vlv_raw_plane_wm_compute()
1865 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id], in vlv_raw_plane_wm_compute()
1866 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]); in vlv_raw_plane_wm_compute()
1875 &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_is_valid()
1877 &crtc_state->wm.vlv.fifo_state; in vlv_raw_plane_wm_is_valid()
1896 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; in vlv_compute_pipe_wm()
1898 &crtc_state->wm.vlv.fifo_state; in vlv_compute_pipe_wm()
1937 &old_crtc_state->wm.vlv.fifo_state; in vlv_compute_pipe_wm()
1959 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_compute_pipe_wm()
1966 wm_state->wm[level].plane[plane_id] = in vlv_compute_pipe_wm()
2005 &crtc_state->wm.vlv.fifo_state; in vlv_atomic_update_fifo()
2098 struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate; in vlv_compute_intermediate_wm()
2099 const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal; in vlv_compute_intermediate_wm()
2104 const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal; in vlv_compute_intermediate_wm()
2122 intermediate->wm[level].plane[plane_id] = in vlv_compute_intermediate_wm()
2123 min(optimal->wm[level].plane[plane_id], in vlv_compute_intermediate_wm()
2124 active->wm[level].plane[plane_id]); in vlv_compute_intermediate_wm()
2141 new_crtc_state->wm.need_postvbl_update = true; in vlv_compute_intermediate_wm()
2147 struct vlv_wm_values *wm) in vlv_merge_wm() argument
2152 wm->level = dev_priv->wm.max_level; in vlv_merge_wm()
2153 wm->cxsr = true; in vlv_merge_wm()
2156 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; in vlv_merge_wm()
2162 wm->cxsr = false; in vlv_merge_wm()
2165 wm->level = min_t(int, wm->level, wm_state->num_levels - 1); in vlv_merge_wm()
2169 wm->cxsr = false; in vlv_merge_wm()
2172 wm->level = VLV_WM_LEVEL_PM2; in vlv_merge_wm()
2175 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; in vlv_merge_wm()
2178 wm->pipe[pipe] = wm_state->wm[wm->level]; in vlv_merge_wm()
2179 if (crtc->active && wm->cxsr) in vlv_merge_wm()
2180 wm->sr = wm_state->sr[wm->level]; in vlv_merge_wm()
2182 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
2183 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
2184 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
2185 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
2191 struct vlv_wm_values *old_wm = &dev_priv->wm.vlv; in vlv_program_watermarks()
2229 mutex_lock(&dev_priv->wm.wm_mutex); in vlv_initial_watermarks()
2230 crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate; in vlv_initial_watermarks()
2232 mutex_unlock(&dev_priv->wm.wm_mutex); in vlv_initial_watermarks()
2242 if (!crtc_state->wm.need_postvbl_update) in vlv_optimize_watermarks()
2245 mutex_lock(&dev_priv->wm.wm_mutex); in vlv_optimize_watermarks()
2246 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; in vlv_optimize_watermarks()
2248 mutex_unlock(&dev_priv->wm.wm_mutex); in vlv_optimize_watermarks()
2822 u16 pri_latency = dev_priv->wm.pri_latency[level]; in ilk_compute_wm_level()
2823 u16 spr_latency = dev_priv->wm.spr_latency[level]; in ilk_compute_wm_level()
2824 u16 cur_latency = dev_priv->wm.cur_latency[level]; in ilk_compute_wm_level()
2849 u16 wm[]) in intel_read_wm_latency() argument
2870 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; in intel_read_wm_latency()
2871 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & in intel_read_wm_latency()
2873 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & in intel_read_wm_latency()
2875 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & in intel_read_wm_latency()
2889 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; in intel_read_wm_latency()
2890 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & in intel_read_wm_latency()
2892 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & in intel_read_wm_latency()
2894 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & in intel_read_wm_latency()
2903 if (wm[level] == 0) { in intel_read_wm_latency()
2905 wm[i] = 0; in intel_read_wm_latency()
2917 if (wm[0] == 0) { in intel_read_wm_latency()
2918 wm[0] += 2; in intel_read_wm_latency()
2920 if (wm[level] == 0) in intel_read_wm_latency()
2922 wm[level] += 2; in intel_read_wm_latency()
2933 wm[0] += 1; in intel_read_wm_latency()
2938 wm[0] = (sskpd >> 56) & 0xFF; in intel_read_wm_latency()
2939 if (wm[0] == 0) in intel_read_wm_latency()
2940 wm[0] = sskpd & 0xF; in intel_read_wm_latency()
2941 wm[1] = (sskpd >> 4) & 0xFF; in intel_read_wm_latency()
2942 wm[2] = (sskpd >> 12) & 0xFF; in intel_read_wm_latency()
2943 wm[3] = (sskpd >> 20) & 0x1FF; in intel_read_wm_latency()
2944 wm[4] = (sskpd >> 32) & 0x1FF; in intel_read_wm_latency()
2948 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; in intel_read_wm_latency()
2949 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; in intel_read_wm_latency()
2950 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; in intel_read_wm_latency()
2951 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; in intel_read_wm_latency()
2956 wm[0] = 7; in intel_read_wm_latency()
2957 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; in intel_read_wm_latency()
2958 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; in intel_read_wm_latency()
2965 u16 wm[5]) in intel_fixup_spr_wm_latency()
2969 wm[0] = 13; in intel_fixup_spr_wm_latency()
2973 u16 wm[5]) in intel_fixup_cur_wm_latency()
2977 wm[0] = 13; in intel_fixup_cur_wm_latency()
2995 const u16 wm[]) in intel_print_wm_latency() argument
3000 unsigned int latency = wm[level]; in intel_print_wm_latency()
3020 wm[level], latency / 10, latency % 10); in intel_print_wm_latency()
3025 u16 wm[5], u16 min) in ilk_increase_wm_latency()
3029 if (wm[0] >= min) in ilk_increase_wm_latency()
3032 wm[0] = max(wm[0], min); in ilk_increase_wm_latency()
3034 wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5)); in ilk_increase_wm_latency()
3047 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12); in snb_wm_latency_quirk()
3048 changed |= ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12); in snb_wm_latency_quirk()
3049 changed |= ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); in snb_wm_latency_quirk()
3056 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); in snb_wm_latency_quirk()
3057 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); in snb_wm_latency_quirk()
3058 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); in snb_wm_latency_quirk()
3074 if (dev_priv->wm.pri_latency[3] == 0 && in snb_wm_lp3_irq_quirk()
3075 dev_priv->wm.spr_latency[3] == 0 && in snb_wm_lp3_irq_quirk()
3076 dev_priv->wm.cur_latency[3] == 0) in snb_wm_lp3_irq_quirk()
3079 dev_priv->wm.pri_latency[3] = 0; in snb_wm_lp3_irq_quirk()
3080 dev_priv->wm.spr_latency[3] = 0; in snb_wm_lp3_irq_quirk()
3081 dev_priv->wm.cur_latency[3] = 0; in snb_wm_lp3_irq_quirk()
3085 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); in snb_wm_lp3_irq_quirk()
3086 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); in snb_wm_lp3_irq_quirk()
3087 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); in snb_wm_lp3_irq_quirk()
3092 intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency); in ilk_setup_wm_latency()
3094 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, in ilk_setup_wm_latency()
3095 sizeof(dev_priv->wm.pri_latency)); in ilk_setup_wm_latency()
3096 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, in ilk_setup_wm_latency()
3097 sizeof(dev_priv->wm.pri_latency)); in ilk_setup_wm_latency()
3099 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency); in ilk_setup_wm_latency()
3100 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency); in ilk_setup_wm_latency()
3102 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); in ilk_setup_wm_latency()
3103 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); in ilk_setup_wm_latency()
3104 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); in ilk_setup_wm_latency()
3114 intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency); in skl_setup_wm_latency()
3115 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency); in skl_setup_wm_latency()
3133 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) { in ilk_validate_pipe_wm()
3155 pipe_wm = &crtc_state->wm.ilk.optimal; in ilk_compute_pipe_wm()
3184 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm)); in ilk_compute_pipe_wm()
3186 pristate, sprstate, curstate, &pipe_wm->wm[0]); in ilk_compute_pipe_wm()
3194 struct intel_wm_level *wm = &pipe_wm->wm[level]; in ilk_compute_pipe_wm() local
3197 pristate, sprstate, curstate, wm); in ilk_compute_pipe_wm()
3204 if (!ilk_validate_wm_level(level, &max, wm)) { in ilk_compute_pipe_wm()
3205 memset(wm, 0, sizeof(*wm)); in ilk_compute_pipe_wm()
3222 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate; in ilk_compute_intermediate_wm()
3227 const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal; in ilk_compute_intermediate_wm()
3235 *a = newstate->wm.ilk.optimal; in ilk_compute_intermediate_wm()
3245 struct intel_wm_level *a_wm = &a->wm[level]; in ilk_compute_intermediate_wm()
3246 const struct intel_wm_level *b_wm = &b->wm[level]; in ilk_compute_intermediate_wm()
3268 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0) in ilk_compute_intermediate_wm()
3269 newstate->wm.need_postvbl_update = true; in ilk_compute_intermediate_wm()
3286 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk; in ilk_merge_wm_level()
3287 const struct intel_wm_level *wm = &active->wm[level]; in ilk_merge_wm_level() local
3297 if (!wm->enable) in ilk_merge_wm_level()
3300 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); in ilk_merge_wm_level()
3301 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); in ilk_merge_wm_level()
3302 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); in ilk_merge_wm_level()
3303 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); in ilk_merge_wm_level()
3328 struct intel_wm_level *wm = &merged->wm[level]; in ilk_wm_merge() local
3330 ilk_merge_wm_level(dev_priv, level, wm); in ilk_wm_merge()
3333 wm->enable = false; in ilk_wm_merge()
3334 else if (!ilk_validate_wm_level(level, max, wm)) in ilk_wm_merge()
3342 if (wm->fbc_val > max->fbc) { in ilk_wm_merge()
3343 if (wm->enable) in ilk_wm_merge()
3345 wm->fbc_val = 0; in ilk_wm_merge()
3358 struct intel_wm_level *wm = &merged->wm[level]; in ilk_wm_merge() local
3360 wm->enable = false; in ilk_wm_merge()
3368 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); in ilk_wm_lp_to_level()
3378 return dev_priv->wm.pri_latency[level]; in ilk_wm_lp_latency()
3398 r = &merged->wm[level]; in ilk_compute_wm_results()
3433 const struct intel_pipe_wm *pipe_wm = &intel_crtc->wm.active.ilk; in ilk_compute_wm_results()
3434 const struct intel_wm_level *r = &pipe_wm->wm[0]; in ilk_compute_wm_results()
3457 if (r1->wm[level].enable) in ilk_find_best_result()
3459 if (r2->wm[level].enable) in ilk_find_best_result()
3531 struct ilk_wm_values *previous = &dev_priv->wm.hw; in _ilk_disable_lp_wm()
3565 struct ilk_wm_values *previous = &dev_priv->wm.hw; in ilk_write_wm_values()
3627 dev_priv->wm.hw = *results; in ilk_write_wm_values()
3890 const struct skl_plane_wm *wm = in skl_crtc_can_enable_sagv() local
3891 &crtc_state->wm.skl.optimal.planes[plane->id]; in skl_crtc_can_enable_sagv()
3894 if (!wm->wm[0].plane_en) in skl_crtc_can_enable_sagv()
3899 !wm->wm[level].plane_en; --level) in skl_crtc_can_enable_sagv()
3902 latency = dev_priv->wm.skl_latency[level]; in skl_crtc_can_enable_sagv()
3931 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in tgl_crtc_can_enable_sagv()
3932 const struct skl_plane_wm *wm = in tgl_crtc_can_enable_sagv() local
3933 &crtc_state->wm.skl.optimal.planes[plane_id]; in tgl_crtc_can_enable_sagv()
3935 if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc) in tgl_crtc_can_enable_sagv()
4012 struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal; in intel_compute_sagv_mask()
4139 !dev_priv->wm.distrust_bios_wm) { in skl_ddb_get_pipe_allocation_limits()
4146 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb; in skl_ddb_get_pipe_allocation_limits()
4263 struct skl_wm_level wm = {}; in skl_cursor_allocation() local
4275 unsigned int latency = dev_priv->wm.skl_latency[level]; in skl_cursor_allocation()
4277 skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm); in skl_cursor_allocation()
4278 if (wm.min_ddb_alloc == U16_MAX) in skl_cursor_allocation()
4281 min_ddb_alloc = wm.min_ddb_alloc; in skl_cursor_allocation()
4784 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; in skl_plane_wm_level()
4785 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; in skl_plane_wm_level() local
4788 return &wm->sagv_wm0; in skl_plane_wm_level()
4790 return &wm->wm[level]; in skl_plane_wm_level()
4798 struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb; in skl_allocate_pipe_ddb()
4812 memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y)); in skl_allocate_pipe_ddb()
4813 memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv)); in skl_allocate_pipe_ddb()
4867 crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start = in skl_allocate_pipe_ddb()
4869 crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end; in skl_allocate_pipe_ddb()
4881 const struct skl_plane_wm *wm = in skl_allocate_pipe_ddb() local
4882 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_allocate_pipe_ddb()
4885 if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) { in skl_allocate_pipe_ddb()
4887 wm->wm[level].min_ddb_alloc != U16_MAX); in skl_allocate_pipe_ddb()
4894 blocks += wm->wm[level].min_ddb_alloc; in skl_allocate_pipe_ddb()
4895 blocks += wm->uv_wm[level].min_ddb_alloc; in skl_allocate_pipe_ddb()
4918 const struct skl_plane_wm *wm = in skl_allocate_pipe_ddb() local
4919 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_allocate_pipe_ddb()
4937 total[plane_id] = wm->wm[level].min_ddb_alloc + extra; in skl_allocate_pipe_ddb()
4948 uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra; in skl_allocate_pipe_ddb()
4958 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_allocate_pipe_ddb()
4960 &crtc_state->wm.skl.plane_ddb_uv[plane_id]; in skl_allocate_pipe_ddb()
4991 struct skl_plane_wm *wm = in skl_allocate_pipe_ddb() local
4992 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_allocate_pipe_ddb()
5006 if (wm->wm[level].min_ddb_alloc > total[plane_id] || in skl_allocate_pipe_ddb()
5007 wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id]) in skl_allocate_pipe_ddb()
5008 memset(&wm->wm[level], 0, sizeof(wm->wm[level])); in skl_allocate_pipe_ddb()
5015 level == 1 && wm->wm[0].plane_en) { in skl_allocate_pipe_ddb()
5016 wm->wm[level].plane_res_b = wm->wm[0].plane_res_b; in skl_allocate_pipe_ddb()
5017 wm->wm[level].plane_res_l = wm->wm[0].plane_res_l; in skl_allocate_pipe_ddb()
5018 wm->wm[level].ignore_lines = wm->wm[0].ignore_lines; in skl_allocate_pipe_ddb()
5028 struct skl_plane_wm *wm = in skl_allocate_pipe_ddb() local
5029 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_allocate_pipe_ddb()
5031 if (wm->trans_wm.plane_res_b >= total[plane_id]) in skl_allocate_pipe_ddb()
5032 memset(&wm->trans_wm, 0, sizeof(wm->trans_wm)); in skl_allocate_pipe_ddb()
5393 unsigned int latency = dev_priv->wm.skl_latency[level]; in skl_compute_wm_levels()
5408 struct skl_wm_level *levels = plane_wm->wm; in tgl_compute_sagv_wm()
5409 unsigned int latency = dev_priv->wm.skl_latency[0] + dev_priv->sagv_block_time_us; in tgl_compute_sagv_wm()
5418 struct skl_plane_wm *wm) in skl_compute_transition_wm() argument
5459 wm0_sel_res_b = wm->wm[0].plane_res_b - 1; in skl_compute_transition_wm()
5475 wm->trans_wm.plane_res_b = res_blocks + 1; in skl_compute_transition_wm()
5476 wm->trans_wm.plane_en = true; in skl_compute_transition_wm()
5485 struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_build_plane_wm_single() local
5494 skl_compute_wm_levels(crtc_state, &wm_params, wm->wm); in skl_build_plane_wm_single()
5497 tgl_compute_sagv_wm(crtc_state, &wm_params, wm); in skl_build_plane_wm_single()
5499 skl_compute_transition_wm(crtc_state, &wm_params, wm); in skl_build_plane_wm_single()
5508 struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_build_plane_wm_uv() local
5512 wm->is_planar = true; in skl_build_plane_wm_uv()
5520 skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm); in skl_build_plane_wm_uv()
5593 struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; in skl_build_pipe_wm()
5652 const struct skl_plane_wm *wm = in skl_write_plane_wm() local
5653 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_write_plane_wm()
5655 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_write_plane_wm()
5657 &crtc_state->wm.skl.plane_ddb_uv[plane_id]; in skl_write_plane_wm()
5668 &wm->trans_wm); in skl_write_plane_wm()
5676 if (wm->is_planar) in skl_write_plane_wm()
5692 const struct skl_plane_wm *wm = in skl_write_cursor_wm() local
5693 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_write_cursor_wm()
5695 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_write_cursor_wm()
5705 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm); in skl_write_cursor_wm()
5731 if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level])) in skl_plane_wm_equals()
5772 if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_ddb_add_affected_planes()
5773 &new_crtc_state->wm.skl.plane_ddb_y[plane_id]) && in skl_ddb_add_affected_planes()
5774 skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id], in skl_ddb_add_affected_planes()
5775 &new_crtc_state->wm.skl.plane_ddb_uv[plane_id])) in skl_ddb_add_affected_planes()
5847 old_pipe_wm = &old_crtc_state->wm.skl.optimal; in skl_print_wm_changes()
5848 new_pipe_wm = &new_crtc_state->wm.skl.optimal; in skl_print_wm_changes()
5854 old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_print_wm_changes()
5855 new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_print_wm_changes()
5881 enast(old_wm->wm[0].plane_en), enast(old_wm->wm[1].plane_en), in skl_print_wm_changes()
5882 enast(old_wm->wm[2].plane_en), enast(old_wm->wm[3].plane_en), in skl_print_wm_changes()
5883 enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en), in skl_print_wm_changes()
5884 enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en), in skl_print_wm_changes()
5887 enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en), in skl_print_wm_changes()
5888 enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en), in skl_print_wm_changes()
5889 enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en), in skl_print_wm_changes()
5890 enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en), in skl_print_wm_changes()
5898 enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l, in skl_print_wm_changes()
5899 enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l, in skl_print_wm_changes()
5900 enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l, in skl_print_wm_changes()
5901 enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l, in skl_print_wm_changes()
5902 enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].plane_res_l, in skl_print_wm_changes()
5903 enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].plane_res_l, in skl_print_wm_changes()
5904 enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l, in skl_print_wm_changes()
5905 enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l, in skl_print_wm_changes()
5909 enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l, in skl_print_wm_changes()
5910 enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l, in skl_print_wm_changes()
5911 enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l, in skl_print_wm_changes()
5912 enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l, in skl_print_wm_changes()
5913 enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].plane_res_l, in skl_print_wm_changes()
5914 enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l, in skl_print_wm_changes()
5915 enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l, in skl_print_wm_changes()
5916 enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l, in skl_print_wm_changes()
5924 old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b, in skl_print_wm_changes()
5925 old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b, in skl_print_wm_changes()
5926 old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b, in skl_print_wm_changes()
5927 old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b, in skl_print_wm_changes()
5930 new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b, in skl_print_wm_changes()
5931 new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b, in skl_print_wm_changes()
5932 new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b, in skl_print_wm_changes()
5933 new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b, in skl_print_wm_changes()
5941 old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc, in skl_print_wm_changes()
5942 old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc, in skl_print_wm_changes()
5943 old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc, in skl_print_wm_changes()
5944 old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc, in skl_print_wm_changes()
5947 new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc, in skl_print_wm_changes()
5948 new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc, in skl_print_wm_changes()
5949 new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc, in skl_print_wm_changes()
5950 new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc, in skl_print_wm_changes()
5985 if (dev_priv->wm.distrust_bios_wm) { in skl_ddb_add_affected_pipes()
6080 &old_crtc_state->wm.skl.optimal.planes[plane_id], in skl_wm_add_affected_planes()
6081 &new_crtc_state->wm.skl.optimal.planes[plane_id])) in skl_wm_add_affected_planes()
6150 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk; in ilk_compute_wm_config() local
6152 if (!wm->pipe_enabled) in ilk_compute_wm_config()
6155 config->sprites_enabled |= wm->sprites_enabled; in ilk_compute_wm_config()
6156 config->sprites_scaled |= wm->sprites_scaled; in ilk_compute_wm_config()
6200 mutex_lock(&dev_priv->wm.wm_mutex); in ilk_initial_watermarks()
6201 crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate; in ilk_initial_watermarks()
6203 mutex_unlock(&dev_priv->wm.wm_mutex); in ilk_initial_watermarks()
6213 if (!crtc_state->wm.need_postvbl_update) in ilk_optimize_watermarks()
6216 mutex_lock(&dev_priv->wm.wm_mutex); in ilk_optimize_watermarks()
6217 crtc->wm.active.ilk = crtc_state->wm.ilk.optimal; in ilk_optimize_watermarks()
6219 mutex_unlock(&dev_priv->wm.wm_mutex); in ilk_optimize_watermarks()
6243 struct skl_plane_wm *wm = &out->planes[plane_id]; in skl_pipe_wm_get_hw_state() local
6251 skl_wm_level_from_reg_val(val, &wm->wm[level]); in skl_pipe_wm_get_hw_state()
6255 wm->sagv_wm0 = wm->wm[0]; in skl_pipe_wm_get_hw_state()
6262 skl_wm_level_from_reg_val(val, &wm->trans_wm); in skl_pipe_wm_get_hw_state()
6277 skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal); in skl_wm_get_hw_state()
6282 dev_priv->wm.distrust_bios_wm = true; in skl_wm_get_hw_state()
6290 struct ilk_wm_values *hw = &dev_priv->wm.hw; in ilk_pipe_wm_get_hw_state()
6292 struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal; in ilk_pipe_wm_get_hw_state()
6315 active->wm[0].enable = true; in ilk_pipe_wm_get_hw_state()
6316 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; in ilk_pipe_wm_get_hw_state()
6317 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; in ilk_pipe_wm_get_hw_state()
6318 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; in ilk_pipe_wm_get_hw_state()
6328 active->wm[level].enable = true; in ilk_pipe_wm_get_hw_state()
6331 crtc->wm.active.ilk = *active; in ilk_pipe_wm_get_hw_state()
6340 struct g4x_wm_values *wm) in g4x_read_wm_values() argument
6345 wm->sr.plane = _FW_WM(tmp, SR); in g4x_read_wm_values()
6346 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); in g4x_read_wm_values()
6347 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB); in g4x_read_wm_values()
6348 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA); in g4x_read_wm_values()
6351 wm->fbc_en = tmp & DSPFW_FBC_SR_EN; in g4x_read_wm_values()
6352 wm->sr.fbc = _FW_WM(tmp, FBC_SR); in g4x_read_wm_values()
6353 wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR); in g4x_read_wm_values()
6354 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB); in g4x_read_wm_values()
6355 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); in g4x_read_wm_values()
6356 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA); in g4x_read_wm_values()
6359 wm->hpll_en = tmp & DSPFW_HPLL_SR_EN; in g4x_read_wm_values()
6360 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); in g4x_read_wm_values()
6361 wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR); in g4x_read_wm_values()
6362 wm->hpll.plane = _FW_WM(tmp, HPLL_SR); in g4x_read_wm_values()
6366 struct vlv_wm_values *wm) in vlv_read_wm_values() argument
6374 wm->ddl[pipe].plane[PLANE_PRIMARY] = in vlv_read_wm_values()
6376 wm->ddl[pipe].plane[PLANE_CURSOR] = in vlv_read_wm_values()
6378 wm->ddl[pipe].plane[PLANE_SPRITE0] = in vlv_read_wm_values()
6380 wm->ddl[pipe].plane[PLANE_SPRITE1] = in vlv_read_wm_values()
6385 wm->sr.plane = _FW_WM(tmp, SR); in vlv_read_wm_values()
6386 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); in vlv_read_wm_values()
6387 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB); in vlv_read_wm_values()
6388 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA); in vlv_read_wm_values()
6391 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB); in vlv_read_wm_values()
6392 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); in vlv_read_wm_values()
6393 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA); in vlv_read_wm_values()
6396 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); in vlv_read_wm_values()
6400 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); in vlv_read_wm_values()
6401 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); in vlv_read_wm_values()
6404 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF); in vlv_read_wm_values()
6405 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE); in vlv_read_wm_values()
6408 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC); in vlv_read_wm_values()
6409 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC); in vlv_read_wm_values()
6412 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; in vlv_read_wm_values()
6413 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8; in vlv_read_wm_values()
6414 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8; in vlv_read_wm_values()
6415 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8; in vlv_read_wm_values()
6416 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; in vlv_read_wm_values()
6417 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; in vlv_read_wm_values()
6418 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; in vlv_read_wm_values()
6419 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; in vlv_read_wm_values()
6420 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; in vlv_read_wm_values()
6421 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; in vlv_read_wm_values()
6424 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); in vlv_read_wm_values()
6425 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); in vlv_read_wm_values()
6428 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; in vlv_read_wm_values()
6429 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; in vlv_read_wm_values()
6430 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; in vlv_read_wm_values()
6431 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; in vlv_read_wm_values()
6432 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; in vlv_read_wm_values()
6433 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; in vlv_read_wm_values()
6434 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; in vlv_read_wm_values()
6443 struct g4x_wm_values *wm = &dev_priv->wm.g4x; in g4x_wm_get_hw_state() local
6446 g4x_read_wm_values(dev_priv, wm); in g4x_wm_get_hw_state()
6448 wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; in g4x_wm_get_hw_state()
6453 struct g4x_wm_state *active = &crtc->wm.active.g4x; in g4x_wm_get_hw_state()
6459 active->cxsr = wm->cxsr; in g4x_wm_get_hw_state()
6460 active->hpll_en = wm->hpll_en; in g4x_wm_get_hw_state()
6461 active->fbc_en = wm->fbc_en; in g4x_wm_get_hw_state()
6463 active->sr = wm->sr; in g4x_wm_get_hw_state()
6464 active->hpll = wm->hpll; in g4x_wm_get_hw_state()
6467 active->wm.plane[plane_id] = in g4x_wm_get_hw_state()
6468 wm->pipe[pipe].plane[plane_id]; in g4x_wm_get_hw_state()
6471 if (wm->cxsr && wm->hpll_en) in g4x_wm_get_hw_state()
6473 else if (wm->cxsr) in g4x_wm_get_hw_state()
6479 raw = &crtc_state->wm.g4x.raw[level]; in g4x_wm_get_hw_state()
6481 raw->plane[plane_id] = active->wm.plane[plane_id]; in g4x_wm_get_hw_state()
6486 raw = &crtc_state->wm.g4x.raw[level]; in g4x_wm_get_hw_state()
6495 raw = &crtc_state->wm.g4x.raw[level]; in g4x_wm_get_hw_state()
6507 crtc_state->wm.g4x.optimal = *active; in g4x_wm_get_hw_state()
6508 crtc_state->wm.g4x.intermediate = *active; in g4x_wm_get_hw_state()
6513 wm->pipe[pipe].plane[PLANE_PRIMARY], in g4x_wm_get_hw_state()
6514 wm->pipe[pipe].plane[PLANE_CURSOR], in g4x_wm_get_hw_state()
6515 wm->pipe[pipe].plane[PLANE_SPRITE0]); in g4x_wm_get_hw_state()
6520 wm->sr.plane, wm->sr.cursor, wm->sr.fbc); in g4x_wm_get_hw_state()
6523 wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc); in g4x_wm_get_hw_state()
6525 yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en)); in g4x_wm_get_hw_state()
6533 mutex_lock(&dev_priv->wm.wm_mutex); in g4x_wm_sanitize()
6542 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; in g4x_wm_sanitize()
6551 &crtc_state->wm.g4x.raw[level]; in g4x_wm_sanitize()
6554 wm_state->wm.plane[plane_id] = 0; in g4x_wm_sanitize()
6560 &crtc_state->wm.g4x.raw[level]; in g4x_wm_sanitize()
6574 crtc_state->wm.g4x.intermediate = in g4x_wm_sanitize()
6575 crtc_state->wm.g4x.optimal; in g4x_wm_sanitize()
6576 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; in g4x_wm_sanitize()
6581 mutex_unlock(&dev_priv->wm.wm_mutex); in g4x_wm_sanitize()
6586 struct vlv_wm_values *wm = &dev_priv->wm.vlv; in vlv_wm_get_hw_state() local
6590 vlv_read_wm_values(dev_priv, wm); in vlv_wm_get_hw_state()
6592 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; in vlv_wm_get_hw_state()
6593 wm->level = VLV_WM_LEVEL_PM2; in vlv_wm_get_hw_state()
6600 wm->level = VLV_WM_LEVEL_PM5; in vlv_wm_get_hw_state()
6620 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; in vlv_wm_get_hw_state()
6624 wm->level = VLV_WM_LEVEL_DDR_DVFS; in vlv_wm_get_hw_state()
6633 struct vlv_wm_state *active = &crtc->wm.active.vlv; in vlv_wm_get_hw_state()
6635 &crtc_state->wm.vlv.fifo_state; in vlv_wm_get_hw_state()
6642 active->num_levels = wm->level + 1; in vlv_wm_get_hw_state()
6643 active->cxsr = wm->cxsr; in vlv_wm_get_hw_state()
6647 &crtc_state->wm.vlv.raw[level]; in vlv_wm_get_hw_state()
6649 active->sr[level].plane = wm->sr.plane; in vlv_wm_get_hw_state()
6650 active->sr[level].cursor = wm->sr.cursor; in vlv_wm_get_hw_state()
6653 active->wm[level].plane[plane_id] = in vlv_wm_get_hw_state()
6654 wm->pipe[pipe].plane[plane_id]; in vlv_wm_get_hw_state()
6657 vlv_invert_wm_value(active->wm[level].plane[plane_id], in vlv_wm_get_hw_state()
6667 crtc_state->wm.vlv.optimal = *active; in vlv_wm_get_hw_state()
6668 crtc_state->wm.vlv.intermediate = *active; in vlv_wm_get_hw_state()
6673 wm->pipe[pipe].plane[PLANE_PRIMARY], in vlv_wm_get_hw_state()
6674 wm->pipe[pipe].plane[PLANE_CURSOR], in vlv_wm_get_hw_state()
6675 wm->pipe[pipe].plane[PLANE_SPRITE0], in vlv_wm_get_hw_state()
6676 wm->pipe[pipe].plane[PLANE_SPRITE1]); in vlv_wm_get_hw_state()
6681 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); in vlv_wm_get_hw_state()
6689 mutex_lock(&dev_priv->wm.wm_mutex); in vlv_wm_sanitize()
6698 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; in vlv_wm_sanitize()
6700 &crtc_state->wm.vlv.fifo_state; in vlv_wm_sanitize()
6709 &crtc_state->wm.vlv.raw[level]; in vlv_wm_sanitize()
6713 wm_state->wm[level].plane[plane_id] = in vlv_wm_sanitize()
6723 crtc_state->wm.vlv.intermediate = in vlv_wm_sanitize()
6724 crtc_state->wm.vlv.optimal; in vlv_wm_sanitize()
6725 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; in vlv_wm_sanitize()
6730 mutex_unlock(&dev_priv->wm.wm_mutex); in vlv_wm_sanitize()
6751 struct ilk_wm_values *hw = &dev_priv->wm.hw; in ilk_wm_get_hw_state()
7651 if ((IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] && in intel_init_pm()
7652 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || in intel_init_pm()
7653 (!IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] && in intel_init_pm()
7654 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { in intel_init_pm()