Lines Matching refs:vlv

458 		dev_priv->wm.vlv.cxsr = enable;  in intel_set_memory_cxsr()
489 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_get_fifo_size()
1705 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2]; in vlv_compute_fifo()
1706 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_compute_fifo()
1820 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_set()
1845 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_compute()
1864 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id], in vlv_raw_plane_wm_compute()
1865 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id], in vlv_raw_plane_wm_compute()
1866 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]); in vlv_raw_plane_wm_compute()
1875 &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_is_valid()
1877 &crtc_state->wm.vlv.fifo_state; in vlv_raw_plane_wm_is_valid()
1896 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; in vlv_compute_pipe_wm()
1898 &crtc_state->wm.vlv.fifo_state; in vlv_compute_pipe_wm()
1937 &old_crtc_state->wm.vlv.fifo_state; in vlv_compute_pipe_wm()
1959 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_compute_pipe_wm()
2005 &crtc_state->wm.vlv.fifo_state; in vlv_atomic_update_fifo()
2098 struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate; in vlv_compute_intermediate_wm()
2099 const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal; in vlv_compute_intermediate_wm()
2104 const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal; in vlv_compute_intermediate_wm()
2156 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; in vlv_merge_wm()
2175 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; in vlv_merge_wm()
2191 struct vlv_wm_values *old_wm = &dev_priv->wm.vlv; in vlv_program_watermarks()
2230 crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate; in vlv_initial_watermarks()
2246 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; in vlv_optimize_watermarks()
6586 struct vlv_wm_values *wm = &dev_priv->wm.vlv; in vlv_wm_get_hw_state()
6633 struct vlv_wm_state *active = &crtc->wm.active.vlv; in vlv_wm_get_hw_state()
6635 &crtc_state->wm.vlv.fifo_state; in vlv_wm_get_hw_state()
6647 &crtc_state->wm.vlv.raw[level]; in vlv_wm_get_hw_state()
6667 crtc_state->wm.vlv.optimal = *active; in vlv_wm_get_hw_state()
6668 crtc_state->wm.vlv.intermediate = *active; in vlv_wm_get_hw_state()
6698 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; in vlv_wm_sanitize()
6700 &crtc_state->wm.vlv.fifo_state; in vlv_wm_sanitize()
6709 &crtc_state->wm.vlv.raw[level]; in vlv_wm_sanitize()
6723 crtc_state->wm.vlv.intermediate = in vlv_wm_sanitize()
6724 crtc_state->wm.vlv.optimal; in vlv_wm_sanitize()
6725 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; in vlv_wm_sanitize()