460 		dev_priv->wm.g4x.cxsr = enable;  in intel_set_memory_cxsr()
1200 		struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];  in g4x_raw_plane_wm_set()
1219 		struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];  in g4x_raw_fbc_wm_set()
1250 		struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];  in g4x_raw_plane_wm_compute()
1292 			    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],  in g4x_raw_plane_wm_compute()
1293 			    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],  in g4x_raw_plane_wm_compute()
1294 			    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);  in g4x_raw_plane_wm_compute()
1299 				    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,  in g4x_raw_plane_wm_compute()
1300 				    crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);  in g4x_raw_plane_wm_compute()
1309 	const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];  in g4x_raw_plane_wm_is_valid()
1375 	struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;  in g4x_compute_pipe_wm()
1404 	raw = &crtc_state->wm.g4x.raw[level];  in g4x_compute_pipe_wm()
1412 	raw = &crtc_state->wm.g4x.raw[level];  in g4x_compute_pipe_wm()
1423 	raw = &crtc_state->wm.g4x.raw[level];  in g4x_compute_pipe_wm()
1455 	struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;  in g4x_compute_intermediate_wm()
1456 	const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;  in g4x_compute_intermediate_wm()
1461 	const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;  in g4x_compute_intermediate_wm()
1543 		const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;  in g4x_merge_wm()
1565 		const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;  in g4x_merge_wm()
1578 	struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;  in g4x_program_watermarks()
1605 	crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;  in g4x_initial_watermarks()
1621 	crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;  in g4x_optimize_watermarks()
6443 	struct g4x_wm_values *wm = &dev_priv->wm.g4x;  in g4x_wm_get_hw_state()
6453 		struct g4x_wm_state *active = &crtc->wm.active.g4x;  in g4x_wm_get_hw_state()
6479 		raw = &crtc_state->wm.g4x.raw[level];  in g4x_wm_get_hw_state()
6486 		raw = &crtc_state->wm.g4x.raw[level];  in g4x_wm_get_hw_state()
6495 		raw = &crtc_state->wm.g4x.raw[level];  in g4x_wm_get_hw_state()
6507 		crtc_state->wm.g4x.optimal = *active;  in g4x_wm_get_hw_state()
6508 		crtc_state->wm.g4x.intermediate = *active;  in g4x_wm_get_hw_state()
6542 		struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;  in g4x_wm_sanitize()
6551 				&crtc_state->wm.g4x.raw[level];  in g4x_wm_sanitize()
6560 					&crtc_state->wm.g4x.raw[level];  in g4x_wm_sanitize()
6574 		crtc_state->wm.g4x.intermediate =  in g4x_wm_sanitize()
6575 			crtc_state->wm.g4x.optimal;  in g4x_wm_sanitize()
6576 		crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;  in g4x_wm_sanitize()