112 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)  argument
126 #define vgpu_opregion(vgpu) (&(vgpu->opregion))  argument
145 	int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
146 	void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
147 	void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
217 static inline void *intel_vgpu_vdev(struct intel_vgpu *vgpu)  in intel_vgpu_vdev()  argument
219 	return vgpu->vdev;  in intel_vgpu_vdev()
389 #define vgpu_aperture_offset(vgpu)	((vgpu)->gm.low_gm_node.start)  argument
390 #define vgpu_hidden_offset(vgpu)	((vgpu)->gm.high_gm_node.start)  argument
391 #define vgpu_aperture_sz(vgpu)		((vgpu)->gm.aperture_sz)  argument
392 #define vgpu_hidden_sz(vgpu)		((vgpu)->gm.hidden_sz)  argument
394 #define vgpu_aperture_pa_base(vgpu) \  argument
395 	(gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
397 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)  argument
399 #define vgpu_aperture_pa_end(vgpu) \  argument
400 	(vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
402 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu))  argument
403 #define vgpu_aperture_gmadr_end(vgpu) \  argument
404 	(vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
406 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu))  argument
407 #define vgpu_hidden_gmadr_end(vgpu) \  argument
408 	(vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
410 #define vgpu_fence_base(vgpu) (vgpu->fence.base)  argument
411 #define vgpu_fence_sz(vgpu) (vgpu->fence.size)  argument
425 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
427 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu);
428 void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
429 void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
434 #define vgpu_vreg_t(vgpu, reg) \  argument
435 	(*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
436 #define vgpu_vreg(vgpu, offset) \  argument
437 	(*(u32 *)(vgpu->mmio.vreg + (offset)))
438 #define vgpu_vreg64_t(vgpu, reg) \  argument
439 	(*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
440 #define vgpu_vreg64(vgpu, offset) \  argument
441 	(*(u64 *)(vgpu->mmio.vreg + (offset)))
443 #define for_each_active_vgpu(gvt, vgpu, id) \  argument
444 	idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
445 		for_each_if(vgpu->active)
447 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,  in intel_vgpu_write_pci_bar()  argument
454 	pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);  in intel_vgpu_write_pci_bar()
471 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu);
474 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);
475 void intel_gvt_release_vgpu(struct intel_vgpu *vgpu);
476 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
478 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu);
479 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu);
480 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu);
483 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \  argument
484 	((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \
485 	 (gmadr <= vgpu_aperture_gmadr_end(vgpu)))
487 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \  argument
488 	((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \
489 	 (gmadr <= vgpu_hidden_gmadr_end(vgpu)))
491 #define vgpu_gmadr_is_valid(vgpu, gmadr) \  argument
492 	 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \
493 	  (vgpu_gmadr_is_hidden(vgpu, gmadr))))
507 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);
508 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr);
509 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr);
510 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
512 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
515 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
517 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu);
519 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
522 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
525 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected);
527 static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar)  in intel_vgpu_get_bar_gpa()  argument
530 	return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &  in intel_vgpu_get_bar_gpa()
534 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu);
535 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu);
536 int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa);
538 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);
539 void populate_pvinfo_page(struct intel_vgpu *vgpu);
542 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason);
555 	void (*vgpu_destroy)(struct intel_vgpu *vgpu);
556 	void (*vgpu_release)(struct intel_vgpu *vgpu);
563 	int (*vgpu_query_plane)(struct intel_vgpu *vgpu, void *);
564 	int (*vgpu_get_dmabuf)(struct intel_vgpu *vgpu, unsigned int);
567 	void (*emulate_hotplug)(struct intel_vgpu *vgpu, bool connected);
683 void intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu);
684 void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu);