38 static int get_edp_pipe(struct intel_vgpu *vgpu)  in get_edp_pipe()  argument
40 	u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);  in get_edp_pipe()
58 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)  in edp_pipe_is_enabled()  argument
60 	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;  in edp_pipe_is_enabled()
62 	if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))  in edp_pipe_is_enabled()
65 	if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))  in edp_pipe_is_enabled()
70 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)  in pipe_is_enabled()  argument
72 	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;  in pipe_is_enabled()
78 	if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)  in pipe_is_enabled()
81 	if (edp_pipe_is_enabled(vgpu) &&  in pipe_is_enabled()
82 			get_edp_pipe(vgpu) == pipe)  in pipe_is_enabled()
170 static void emulate_monitor_status_change(struct intel_vgpu *vgpu)  in emulate_monitor_status_change()  argument
172 	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;  in emulate_monitor_status_change()
180 		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |  in emulate_monitor_status_change()
185 			vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=  in emulate_monitor_status_change()
187 			vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;  in emulate_monitor_status_change()
188 			vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;  in emulate_monitor_status_change()
189 			vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;  in emulate_monitor_status_change()
190 			vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;  in emulate_monitor_status_change()
194 			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &=  in emulate_monitor_status_change()
198 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=  in emulate_monitor_status_change()
203 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=  in emulate_monitor_status_change()
205 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=  in emulate_monitor_status_change()
209 			vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=  in emulate_monitor_status_change()
214 			vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=  in emulate_monitor_status_change()
217 			vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;  in emulate_monitor_status_change()
219 		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=  in emulate_monitor_status_change()
221 		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=  in emulate_monitor_status_change()
223 		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=  in emulate_monitor_status_change()
226 		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;  in emulate_monitor_status_change()
227 		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;  in emulate_monitor_status_change()
229 		vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));  in emulate_monitor_status_change()
230 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=  in emulate_monitor_status_change()
232 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=  in emulate_monitor_status_change()
234 		vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);  in emulate_monitor_status_change()
235 		vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);  in emulate_monitor_status_change()
237 		vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;  in emulate_monitor_status_change()
238 		vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;  in emulate_monitor_status_change()
246 		vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;  in emulate_monitor_status_change()
247 		vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE;  in emulate_monitor_status_change()
255 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;  in emulate_monitor_status_change()
256 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;  in emulate_monitor_status_change()
257 		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;  in emulate_monitor_status_change()
258 		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;  in emulate_monitor_status_change()
259 		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;  in emulate_monitor_status_change()
262 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {  in emulate_monitor_status_change()
263 			vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);  in emulate_monitor_status_change()
264 			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=  in emulate_monitor_status_change()
266 			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=  in emulate_monitor_status_change()
268 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=  in emulate_monitor_status_change()
270 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=  in emulate_monitor_status_change()
273 			vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=  in emulate_monitor_status_change()
277 			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=  in emulate_monitor_status_change()
279 			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=  in emulate_monitor_status_change()
281 			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=  in emulate_monitor_status_change()
284 			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=  in emulate_monitor_status_change()
286 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=  in emulate_monitor_status_change()
290 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {  in emulate_monitor_status_change()
291 			vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;  in emulate_monitor_status_change()
292 			vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);  in emulate_monitor_status_change()
293 			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=  in emulate_monitor_status_change()
295 			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=  in emulate_monitor_status_change()
297 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=  in emulate_monitor_status_change()
299 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=  in emulate_monitor_status_change()
302 			vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=  in emulate_monitor_status_change()
306 			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=  in emulate_monitor_status_change()
308 			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=  in emulate_monitor_status_change()
310 			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=  in emulate_monitor_status_change()
314 			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=  in emulate_monitor_status_change()
316 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=  in emulate_monitor_status_change()
320 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {  in emulate_monitor_status_change()
321 			vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;  in emulate_monitor_status_change()
322 			vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);  in emulate_monitor_status_change()
323 			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=  in emulate_monitor_status_change()
325 			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=  in emulate_monitor_status_change()
327 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=  in emulate_monitor_status_change()
329 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=  in emulate_monitor_status_change()
332 			vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=  in emulate_monitor_status_change()
336 			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=  in emulate_monitor_status_change()
338 			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=  in emulate_monitor_status_change()
340 			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=  in emulate_monitor_status_change()
344 			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=  in emulate_monitor_status_change()
346 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=  in emulate_monitor_status_change()
353 	vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |  in emulate_monitor_status_change()
361 		vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |  in emulate_monitor_status_change()
363 		vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=  in emulate_monitor_status_change()
376 		vgpu_vreg_t(vgpu, DPLL_CTRL1) =  in emulate_monitor_status_change()
378 		vgpu_vreg_t(vgpu, DPLL_CTRL1) |=  in emulate_monitor_status_change()
380 		vgpu_vreg_t(vgpu, LCPLL1_CTL) =  in emulate_monitor_status_change()
382 		vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);  in emulate_monitor_status_change()
389 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;  in emulate_monitor_status_change()
390 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;  in emulate_monitor_status_change()
391 		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;  in emulate_monitor_status_change()
392 		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;  in emulate_monitor_status_change()
393 		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;  in emulate_monitor_status_change()
396 	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {  in emulate_monitor_status_change()
397 		vgpu_vreg_t(vgpu, DPLL_CTRL2) &=  in emulate_monitor_status_change()
399 		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=  in emulate_monitor_status_change()
401 		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=  in emulate_monitor_status_change()
403 		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;  in emulate_monitor_status_change()
404 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=  in emulate_monitor_status_change()
407 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=  in emulate_monitor_status_change()
412 			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=  in emulate_monitor_status_change()
414 			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=  in emulate_monitor_status_change()
417 		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;  in emulate_monitor_status_change()
418 		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;  in emulate_monitor_status_change()
419 		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;  in emulate_monitor_status_change()
422 	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {  in emulate_monitor_status_change()
423 		vgpu_vreg_t(vgpu, DPLL_CTRL2) &=  in emulate_monitor_status_change()
425 		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=  in emulate_monitor_status_change()
427 		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=  in emulate_monitor_status_change()
429 		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;  in emulate_monitor_status_change()
430 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=  in emulate_monitor_status_change()
433 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=  in emulate_monitor_status_change()
438 			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=  in emulate_monitor_status_change()
440 			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=  in emulate_monitor_status_change()
443 		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;  in emulate_monitor_status_change()
444 		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;  in emulate_monitor_status_change()
445 		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;  in emulate_monitor_status_change()
448 	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {  in emulate_monitor_status_change()
449 		vgpu_vreg_t(vgpu, DPLL_CTRL2) &=  in emulate_monitor_status_change()
451 		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=  in emulate_monitor_status_change()
453 		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=  in emulate_monitor_status_change()
455 		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;  in emulate_monitor_status_change()
456 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=  in emulate_monitor_status_change()
459 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=  in emulate_monitor_status_change()
464 			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=  in emulate_monitor_status_change()
466 			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=  in emulate_monitor_status_change()
469 		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;  in emulate_monitor_status_change()
470 		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;  in emulate_monitor_status_change()
471 		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;  in emulate_monitor_status_change()
478 			intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {  in emulate_monitor_status_change()
479 		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;  in emulate_monitor_status_change()
482 	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {  in emulate_monitor_status_change()
484 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=  in emulate_monitor_status_change()
487 			vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;  in emulate_monitor_status_change()
489 		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;  in emulate_monitor_status_change()
494 		vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;  in emulate_monitor_status_change()
498 		vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;  in emulate_monitor_status_change()
499 		vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;  in emulate_monitor_status_change()
500 		vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;  in emulate_monitor_status_change()
501 		vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;  in emulate_monitor_status_change()
504 	vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;  in emulate_monitor_status_change()
507 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)  in clean_virtual_dp_monitor()  argument
509 	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);  in clean_virtual_dp_monitor()
518 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,  in setup_virtual_dp_monitor()  argument
521 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in setup_virtual_dp_monitor()
522 	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);  in setup_virtual_dp_monitor()
547 	emulate_monitor_status_change(vgpu);  in setup_virtual_dp_monitor()
564 	struct intel_vgpu *vgpu;  in intel_gvt_check_vblank_emulation()  local
569 	for_each_active_vgpu(gvt, vgpu, id) {  in intel_gvt_check_vblank_emulation()
571 			if (pipe_is_enabled(vgpu, pipe)) {  in intel_gvt_check_vblank_emulation()
590 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)  in emulate_vblank_on_pipe()  argument
592 	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;  in emulate_vblank_on_pipe()
593 	struct intel_vgpu_irq *irq = &vgpu->irq;  in emulate_vblank_on_pipe()
607 		if (!pipe_is_enabled(vgpu, pipe))  in emulate_vblank_on_pipe()
610 		intel_vgpu_trigger_virtual_event(vgpu, event);  in emulate_vblank_on_pipe()
613 	if (pipe_is_enabled(vgpu, pipe)) {  in emulate_vblank_on_pipe()
614 		vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;  in emulate_vblank_on_pipe()
615 		intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);  in emulate_vblank_on_pipe()
619 static void emulate_vblank(struct intel_vgpu *vgpu)  in emulate_vblank()  argument
623 	mutex_lock(&vgpu->vgpu_lock);  in emulate_vblank()
624 	for_each_pipe(vgpu->gvt->gt->i915, pipe)  in emulate_vblank()
625 		emulate_vblank_on_pipe(vgpu, pipe);  in emulate_vblank()
626 	mutex_unlock(&vgpu->vgpu_lock);  in emulate_vblank()
638 	struct intel_vgpu *vgpu;  in intel_gvt_emulate_vblank()  local
642 	for_each_active_vgpu(gvt, vgpu, id)  in intel_gvt_emulate_vblank()
643 		emulate_vblank(vgpu);  in intel_gvt_emulate_vblank()
655 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)  in intel_vgpu_emulate_hotplug()  argument
657 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in intel_vgpu_emulate_hotplug()
665 			vgpu_vreg_t(vgpu, SFUSE_STRAP) |=  in intel_vgpu_emulate_hotplug()
667 			vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;  in intel_vgpu_emulate_hotplug()
669 			vgpu_vreg_t(vgpu, SFUSE_STRAP) &=  in intel_vgpu_emulate_hotplug()
671 			vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;  in intel_vgpu_emulate_hotplug()
673 		vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;  in intel_vgpu_emulate_hotplug()
674 		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=  in intel_vgpu_emulate_hotplug()
676 		intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);  in intel_vgpu_emulate_hotplug()
678 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {  in intel_vgpu_emulate_hotplug()
680 				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=  in intel_vgpu_emulate_hotplug()
683 				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=  in intel_vgpu_emulate_hotplug()
686 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=  in intel_vgpu_emulate_hotplug()
688 			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=  in intel_vgpu_emulate_hotplug()
690 			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=  in intel_vgpu_emulate_hotplug()
692 			intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG);  in intel_vgpu_emulate_hotplug()
694 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {  in intel_vgpu_emulate_hotplug()
696 				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=  in intel_vgpu_emulate_hotplug()
698 				vgpu_vreg_t(vgpu, SFUSE_STRAP) |=  in intel_vgpu_emulate_hotplug()
701 				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=  in intel_vgpu_emulate_hotplug()
703 				vgpu_vreg_t(vgpu, SFUSE_STRAP) &=  in intel_vgpu_emulate_hotplug()
706 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=  in intel_vgpu_emulate_hotplug()
708 			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=  in intel_vgpu_emulate_hotplug()
710 			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=  in intel_vgpu_emulate_hotplug()
712 			intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);  in intel_vgpu_emulate_hotplug()
714 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {  in intel_vgpu_emulate_hotplug()
716 				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=  in intel_vgpu_emulate_hotplug()
718 				vgpu_vreg_t(vgpu, SFUSE_STRAP) |=  in intel_vgpu_emulate_hotplug()
721 				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=  in intel_vgpu_emulate_hotplug()
723 				vgpu_vreg_t(vgpu, SFUSE_STRAP) &=  in intel_vgpu_emulate_hotplug()
726 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=  in intel_vgpu_emulate_hotplug()
728 			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=  in intel_vgpu_emulate_hotplug()
730 			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=  in intel_vgpu_emulate_hotplug()
732 			intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG);  in intel_vgpu_emulate_hotplug()
744 void intel_vgpu_clean_display(struct intel_vgpu *vgpu)  in intel_vgpu_clean_display()  argument
746 	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;  in intel_vgpu_clean_display()
752 		clean_virtual_dp_monitor(vgpu, PORT_D);  in intel_vgpu_clean_display()
754 		clean_virtual_dp_monitor(vgpu, PORT_B);  in intel_vgpu_clean_display()
768 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)  in intel_vgpu_init_display()  argument
770 	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;  in intel_vgpu_init_display()
772 	intel_vgpu_init_i2c_edid(vgpu);  in intel_vgpu_init_display()
778 		return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,  in intel_vgpu_init_display()
781 		return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,  in intel_vgpu_init_display()
792 void intel_vgpu_reset_display(struct intel_vgpu *vgpu)  in intel_vgpu_reset_display()  argument
794 	emulate_monitor_status_change(vgpu);  in intel_vgpu_reset_display()