Lines Matching refs:dpcd
135 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_clock_recovery_delay()
137 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_link_train_clock_recovery_delay()
144 if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) in drm_dp_link_train_clock_recovery_delay()
153 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_channel_eq_delay()
155 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_link_train_channel_eq_delay()
386 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_is_type()
389 return drm_dp_is_branch(dpcd) && in drm_dp_downstream_is_type()
390 dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_downstream_is_type()
403 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_is_tmds()
407 if (dpcd[DP_DPCD_REV] < 0x11) { in drm_dp_downstream_is_tmds()
408 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { in drm_dp_downstream_is_tmds()
490 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_downstream_port_count()
492 u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK; in drm_dp_downstream_port_count()
494 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4) in drm_dp_downstream_port_count()
501 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_extended_dpcd_caps()
513 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_read_extended_dpcd_caps()
524 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { in drm_dp_read_extended_dpcd_caps()
526 aux->name, dpcd[DP_DPCD_REV], in drm_dp_read_extended_dpcd_caps()
531 if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) in drm_dp_read_extended_dpcd_caps()
535 aux->name, DP_RECEIVER_CAP_SIZE, dpcd); in drm_dp_read_extended_dpcd_caps()
537 memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext)); in drm_dp_read_extended_dpcd_caps()
556 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_read_dpcd_caps()
560 ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); in drm_dp_read_dpcd_caps()
563 if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0) in drm_dp_read_dpcd_caps()
566 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd); in drm_dp_read_dpcd_caps()
571 aux->name, DP_RECEIVER_CAP_SIZE, dpcd); in drm_dp_read_dpcd_caps()
591 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_downstream_info()
600 if (!drm_dp_is_branch(dpcd) || in drm_dp_read_downstream_info()
601 dpcd[DP_DPCD_REV] < DP_DPCD_REV_10 || in drm_dp_read_downstream_info()
602 !(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) in drm_dp_read_downstream_info()
609 len = drm_dp_downstream_port_count(dpcd); in drm_dp_read_downstream_info()
613 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) in drm_dp_read_downstream_info()
637 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_max_dotclock()
640 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_dotclock()
643 if (dpcd[DP_DPCD_REV] < 0x11) in drm_dp_downstream_max_dotclock()
648 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_max_dotclock()
666 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_max_tmds_clock()
670 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_tmds_clock()
673 if (dpcd[DP_DPCD_REV] < 0x11) { in drm_dp_downstream_max_tmds_clock()
674 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { in drm_dp_downstream_max_tmds_clock()
708 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_max_tmds_clock()
712 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_max_tmds_clock()
731 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_min_tmds_clock()
735 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_min_tmds_clock()
738 if (dpcd[DP_DPCD_REV] < 0x11) { in drm_dp_downstream_min_tmds_clock()
739 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { in drm_dp_downstream_min_tmds_clock()
774 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_max_bpc()
778 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_bpc()
781 if (dpcd[DP_DPCD_REV] < 0x11) { in drm_dp_downstream_max_bpc()
782 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { in drm_dp_downstream_max_bpc()
800 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_max_bpc()
830 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_420_passthrough()
833 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_420_passthrough()
836 if (dpcd[DP_DPCD_REV] < 0x13) in drm_dp_downstream_420_passthrough()
843 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_420_passthrough()
861 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_444_to_420_conversion()
864 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_444_to_420_conversion()
867 if (dpcd[DP_DPCD_REV] < 0x13) in drm_dp_downstream_444_to_420_conversion()
872 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) in drm_dp_downstream_444_to_420_conversion()
894 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_mode()
900 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_mode()
903 if (dpcd[DP_DPCD_REV] < 0x11) in drm_dp_downstream_mode()
960 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_debug()
965 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & in drm_dp_downstream_debug()
973 bool branch_device = drm_dp_is_branch(dpcd); in drm_dp_downstream_debug()
1021 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap); in drm_dp_downstream_debug()
1025 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid); in drm_dp_downstream_debug()
1029 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid); in drm_dp_downstream_debug()
1033 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid); in drm_dp_downstream_debug()
1047 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_subconnector_type()
1051 if (!drm_dp_is_branch(dpcd)) in drm_dp_subconnector_type()
1054 if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) { in drm_dp_subconnector_type()
1055 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] & in drm_dp_subconnector_type()
1104 const u8 *dpcd, in drm_dp_set_subconnector_property() argument
1110 subconnector = drm_dp_subconnector_type(dpcd, port_cap); in drm_dp_set_subconnector_property()
1130 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_sink_count_cap()
1135 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 && in drm_dp_read_sink_count_cap()
1136 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && in drm_dp_read_sink_count_cap()