261 	struct clk		*refclk;  member
457 	/* Wait for PLL to lock: up to 2.09 ms, depending on refclk */  in tc_pllupdate()
463 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)  in tc_pxl_pll_en()  argument
477 		refclk);  in tc_pxl_pll_en()
482 		 * refclk / ext_pre_div should be in the 1 to 200 MHz range.  in tc_pxl_pll_en()
483 		 * We don't allow any refclk > 200 MHz, only check lower bounds.  in tc_pxl_pll_en()
485 		if (refclk / ext_div[i_pre] < 1000000)  in tc_pxl_pll_en()
494 				do_div(tmp, refclk);  in tc_pxl_pll_en()
501 				clk = (refclk / ext_div[i_pre] / div) * mul;  in tc_pxl_pll_en()
503 				 * refclk * mul / (ext_pre_div * pre_div)  in tc_pxl_pll_en()
531 	dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,  in tc_pxl_pll_en()
535 	if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)  in tc_pxl_pll_en()
551 	pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */  in tc_pxl_pll_en()
552 	pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */  in tc_pxl_pll_en()
594 	rate = clk_get_rate(tc->refclk);  in tc_set_syspllparam()
609 		dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);  in tc_set_syspllparam()
1176 		ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),  in tc_stream_enable()
1567 	struct clk *refclk = data;  in tc_clk_disable()  local
1569 	clk_disable_unprepare(refclk);  in tc_clk_disable()
1588 	tc->refclk = devm_clk_get(dev, "ref");  in tc_probe()
1589 	if (IS_ERR(tc->refclk)) {  in tc_probe()
1590 		ret = PTR_ERR(tc->refclk);  in tc_probe()
1591 		dev_err(dev, "Failed to get refclk: %d\n", ret);  in tc_probe()
1595 	ret = clk_prepare_enable(tc->refclk);  in tc_probe()
1599 	ret = devm_add_action_or_reset(dev, tc_clk_disable, tc->refclk);  in tc_probe()
1695 			     clk_get_rate(tc->refclk) * 2 / 1000);  in tc_probe()