Lines Matching refs:it6161
948 struct it6161 { struct
1019 static struct it6161 *it6161; argument
1071 static int it6161_mipi_rx_read(struct it6161 *it6161, unsigned int reg_addr) in it6161_mipi_rx_read() argument
1075 struct device *dev = &it6161->i2c_mipi_rx->dev; in it6161_mipi_rx_read()
1077 err = regmap_read(it6161->regmap_mipi_rx, reg_addr, &value); in it6161_mipi_rx_read()
1087 static int mipi_rx_read_word(struct it6161 *it6161, unsigned int reg) in mipi_rx_read_word() argument
1091 val_0 = it6161_mipi_rx_read(it6161, reg); in mipi_rx_read_word()
1096 val_1 = it6161_mipi_rx_read(it6161, reg + 1); in mipi_rx_read_word()
1104 static int it6161_mipi_rx_write(struct it6161 *it6161, unsigned int reg_addr, in it6161_mipi_rx_write() argument
1108 struct device *dev = &it6161->i2c_mipi_rx->dev; in it6161_mipi_rx_write()
1110 err = regmap_write(it6161->regmap_mipi_rx, reg_addr, reg_val); in it6161_mipi_rx_write()
1121 static int it6161_mipi_rx_set_bits(struct it6161 *it6161, unsigned int reg, in it6161_mipi_rx_set_bits() argument
1125 struct device *dev = &it6161->i2c_mipi_rx->dev; in it6161_mipi_rx_set_bits()
1127 err = regmap_update_bits(it6161->regmap_mipi_rx, reg, mask, value); in it6161_mipi_rx_set_bits()
1139 static void it6161_mipi_rx_dump(struct it6161 *it6161)
1148 regs[j] = it6161_mipi_rx_read(it6161, i + j);
1155 static int it6161_hdmi_tx_read(struct it6161 *it6161, unsigned int reg_addr) in it6161_hdmi_tx_read() argument
1159 struct device *dev = &it6161->i2c_mipi_rx->dev; in it6161_hdmi_tx_read()
1161 err = regmap_read(it6161->regmap_hdmi_tx, reg_addr, &value); in it6161_hdmi_tx_read()
1171 static int hdmi_tx_read_word(struct it6161 *it6161, unsigned int reg) in hdmi_tx_read_word() argument
1175 val_0 = it6161_hdmi_tx_read(it6161, reg); in hdmi_tx_read_word()
1180 val_1 = it6161_hdmi_tx_read(it6161, reg + 1); in hdmi_tx_read_word()
1189 static int it6161_hdmi_tx_burst_read(struct it6161 *it6161, unsigned int reg_addr, void *buffer, si… in it6161_hdmi_tx_burst_read() argument
1191 struct device *dev = &it6161->i2c_mipi_rx->dev; in it6161_hdmi_tx_burst_read()
1194 ret = regmap_bulk_read(it6161->regmap_hdmi_tx, reg_addr, buffer, size); in it6161_hdmi_tx_burst_read()
1202 static int it6161_hdmi_tx_write(struct it6161 *it6161, unsigned int reg_addr, in it6161_hdmi_tx_write() argument
1205 struct device *dev = &it6161->i2c_mipi_rx->dev; in it6161_hdmi_tx_write()
1208 err = regmap_write(it6161->regmap_hdmi_tx, reg_addr, reg_val); in it6161_hdmi_tx_write()
1220 static int hdmi_tx_burst_write(struct it6161 *it6161, unsigned int reg_addr,
1223 struct device *dev = &it6161->i2c_hdmi_tx->dev;
1226 ret = regmap_bulk_write(it6161->regmap_hdmi_tx, reg_addr,
1239 static int it6161_hdmi_tx_set_bits(struct it6161 *it6161, unsigned int reg, in it6161_hdmi_tx_set_bits() argument
1243 struct device *dev = &it6161->i2c_mipi_rx->dev; in it6161_hdmi_tx_set_bits()
1245 err = regmap_update_bits(it6161->regmap_hdmi_tx, reg, mask, value); in it6161_hdmi_tx_set_bits()
1256 static int inline it6161_hdmi_tx_change_bank(struct it6161 *it6161, int x) in it6161_hdmi_tx_change_bank() argument
1258 return it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x03, x & 0x03); in it6161_hdmi_tx_change_bank()
1262 static void it6161_hdmi_tx_dump(struct it6161 *it6161, unsigned int bank)
1269 it6161_hdmi_tx_change_bank(it6161, bank);
1273 regs[j] = it6161_hdmi_tx_read(it6161, i + j);
1280 static int it6161_cec_read(struct it6161 *it6161, unsigned int reg_addr) in it6161_cec_read() argument
1284 struct device *dev = &it6161->i2c_mipi_rx->dev; in it6161_cec_read()
1286 err = regmap_read(it6161->regmap_cec, reg_addr, &value); in it6161_cec_read()
1296 static int it6161_cec_write(struct it6161 *it6161, unsigned int reg_addr, in it6161_cec_write() argument
1300 struct device *dev = &it6161->i2c_mipi_rx->dev; in it6161_cec_write()
1302 err = regmap_write(it6161->regmap_cec, reg_addr, reg_val); in it6161_cec_write()
1314 static int it6161_cec_set_bits(struct it6161 *it6161, unsigned int reg,
1318 struct device *dev = &it6161->i2c_mipi_rx->dev;
1320 err = regmap_update_bits(it6161->regmap_cec, reg, mask, value);
1332 static inline struct it6161 *connector_to_it6161(struct drm_connector *c) in connector_to_it6161()
1334 return container_of(c, struct it6161, connector); in connector_to_it6161()
1337 static inline struct it6161 *bridge_to_it6161(struct drm_bridge *bridge) in bridge_to_it6161()
1339 return container_of(bridge, struct it6161, bridge); in bridge_to_it6161()
1342 static void mipi_rx_logic_reset(struct it6161 *it6161) in mipi_rx_logic_reset() argument
1344 it6161_mipi_rx_set_bits(it6161, 0x05, 0x08, 0x08); in mipi_rx_logic_reset()
1347 static void mipi_rx_logic_reset_release(struct it6161 *it6161) in mipi_rx_logic_reset_release() argument
1349 it6161_mipi_rx_set_bits(it6161, 0x05, 0x08, 0x00); in mipi_rx_logic_reset_release()
1352 static void hdmi_tx_logic_reset(struct it6161 *it6161) in hdmi_tx_logic_reset() argument
1354 it6161_hdmi_tx_set_bits(it6161, 0x04, 0x20, 0x20); in hdmi_tx_logic_reset()
1357 static void it6161_mipi_rx_int_mask_disable(struct it6161 *it6161) in it6161_mipi_rx_int_mask_disable() argument
1359 it6161_mipi_rx_set_bits(it6161, 0x0F, 0x03, 0x00); in it6161_mipi_rx_int_mask_disable()
1360 it6161_mipi_rx_write(it6161, 0x09, 0x00); in it6161_mipi_rx_int_mask_disable()
1361 it6161_mipi_rx_write(it6161, 0x0A, 0x00); in it6161_mipi_rx_int_mask_disable()
1362 it6161_mipi_rx_write(it6161, 0x0B, 0x00); in it6161_mipi_rx_int_mask_disable()
1365 static void it6161_mipi_rx_int_mask_enable(struct it6161 *it6161) in it6161_mipi_rx_int_mask_enable() argument
1367 it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x03, 0x00); in it6161_mipi_rx_int_mask_enable()
1368 it6161_mipi_rx_write(it6161, 0x09, EnMBPM ? 0x11 : 0xBF); in it6161_mipi_rx_int_mask_enable()
1369 it6161_mipi_rx_write(it6161, 0x0A, 0xFF); in it6161_mipi_rx_int_mask_enable()
1370 it6161_mipi_rx_write(it6161, 0x0B, 0x3F); in it6161_mipi_rx_int_mask_enable()
1373 static void hdmi_tx_hdcp_int_mask_disable(struct it6161 *it6161) in hdmi_tx_hdcp_int_mask_disable() argument
1375 it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x03, 0x00); in hdmi_tx_hdcp_int_mask_disable()
1376 …it6161_hdmi_tx_set_bits(it6161, REG_TX_INT_MASK2, B_TX_AUTH_FAIL_MASK | B_TX_AUTH_DONE_MASK | B_TX… in hdmi_tx_hdcp_int_mask_disable()
1380 static void hdmi_tx_hdcp_int_mask_enable(struct it6161 *it6161) in hdmi_tx_hdcp_int_mask_enable() argument
1382 it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x03, 0x00); in hdmi_tx_hdcp_int_mask_enable()
1383 …it6161_hdmi_tx_set_bits(it6161, REG_TX_INT_MASK2, B_TX_AUTH_FAIL_MASK | B_TX_AUTH_DONE_MASK | B_TX… in hdmi_tx_hdcp_int_mask_enable()
1395 static void it6161_hdmi_tx_int_mask_enable(struct it6161 *it6161) in it6161_hdmi_tx_int_mask_enable() argument
1397 it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x03, 0x00); in it6161_hdmi_tx_int_mask_enable()
1398 …it6161_hdmi_tx_write(it6161, REG_TX_INT_MASK1, ~(B_TX_AUDIO_OVFLW_MASK | B_TX_DDC_FIFO_ERR_MASK | … in it6161_hdmi_tx_int_mask_enable()
1399 …it6161_hdmi_tx_write(it6161, REG_TX_INT_MASK2, ~(B_TX_AUTH_FAIL_MASK | B_TX_AUTH_DONE_MASK | B_TX_… in it6161_hdmi_tx_int_mask_enable()
1400 it6161_hdmi_tx_write(it6161, REG_TX_INT_MASK3, ~B_TX_VIDSTABLE_MASK); in it6161_hdmi_tx_int_mask_enable()
1403 static void it6161_hdmi_tx_write_table(struct it6161 *it6161, const RegSetEntry table[], int size) in it6161_hdmi_tx_write_table() argument
1411 it6161_hdmi_tx_write(it6161, table[i].offset, in it6161_hdmi_tx_write_table()
1414 it6161_hdmi_tx_set_bits(it6161, table[i].offset, table[i].mask, in it6161_hdmi_tx_write_table()
1420 static inline void hdmi_tx_enable_pattern_generator(struct it6161 *it6161) in hdmi_tx_enable_pattern_generator() argument
1423 it6161_hdmi_tx_set_bits(it6161, 0xA8, 0x01, 0x01); in hdmi_tx_enable_pattern_generator()
1426 static inline void hdmi_tx_disable_pattern_generator(struct it6161 *it6161) in hdmi_tx_disable_pattern_generator() argument
1428 it6161_hdmi_tx_set_bits(it6161, 0xA8, 0x01, 0x00); in hdmi_tx_disable_pattern_generator()
1431 static inline void hdmi_tx_pattern_generator_setup_color(struct it6161 *it6161) in hdmi_tx_pattern_generator_setup_color() argument
1433 …it6161_hdmi_tx_set_bits(it6161, 0xA9, 0x3F, (HDMI_TX_PATTERN_COLLOR_B << 4) | (HDMI_TX_PATTERN_COL… in hdmi_tx_pattern_generator_setup_color()
1436 static void hdmi_tx_setup_pattern_generator(struct it6161 *it6161) in hdmi_tx_setup_pattern_generator() argument
1440 …it6161_hdmi_tx_write_table(it6161, hdmi_tx_pg_480p60_table, sizeof(hdmi_tx_pg_480p60_table) / size… in hdmi_tx_setup_pattern_generator()
1445 …it6161_hdmi_tx_write_table(it6161, hdmi_tx_pg_720p60_table, sizeof(hdmi_tx_pg_720p60_table) / size… in hdmi_tx_setup_pattern_generator()
1450 …it6161_hdmi_tx_write_table(it6161, hdmi_tx_pg_1080p60_table, sizeof(hdmi_tx_pg_1080p60_table) / si… in hdmi_tx_setup_pattern_generator()
1455 …it6161_hdmi_tx_write_table(it6161, hdmi_tx_pg_1080p60_table, sizeof(hdmi_tx_pg_1080p60_table) / si… in hdmi_tx_setup_pattern_generator()
1459 hdmi_tx_pattern_generator_setup_color(it6161); in hdmi_tx_setup_pattern_generator()
1460 hdmi_tx_enable_pattern_generator(it6161); in hdmi_tx_setup_pattern_generator()
1463 static void show_display_mode(struct it6161 *it6161, struct drm_display_mode *display_mode, u8 sele… in show_display_mode() argument
1487 it6161_mipi_rx_set_bits(it6161, 0x0D, 0x02, level == HIGH ? 0x02 : 0x00); in it6161_set_interrupts_active_level()
1488 it6161_hdmi_tx_set_bits(it6161, 0x05, 0xC0, level == HIGH ? 0x80 : 0x40); in it6161_set_interrupts_active_level()
1491 static void hdmi_tx_init(struct it6161 *it6161) in hdmi_tx_init() argument
1495 it6161_hdmi_tx_write_table(it6161, HDMITX_Init_Table, ARRAY_SIZE(HDMITX_Init_Table)); in hdmi_tx_init()
1496 it6161_hdmi_tx_write_table(it6161, HDMITX_PwrOn_Table, ARRAY_SIZE(HDMITX_PwrOn_Table)); in hdmi_tx_init()
1497 …it6161_hdmi_tx_write_table(it6161, HDMITX_DefaultVideo_Table, ARRAY_SIZE(HDMITX_DefaultVideo_Table… in hdmi_tx_init()
1498 it6161_hdmi_tx_write_table(it6161, HDMITX_SetHDMI_Table, ARRAY_SIZE(HDMITX_SetHDMI_Table)); in hdmi_tx_init()
1499 …it6161_hdmi_tx_write_table(it6161, HDMITX_DefaultAVIInfo_Table, ARRAY_SIZE(HDMITX_DefaultAVIInfo_T… in hdmi_tx_init()
1500 …it6161_hdmi_tx_write_table(it6161, HDMITX_DeaultAudioInfo_Table, ARRAY_SIZE(HDMITX_DeaultAudioInfo… in hdmi_tx_init()
1501 …it6161_hdmi_tx_write_table(it6161, HDMITX_Aud_CHStatus_LPCM_20bit_48Khz, ARRAY_SIZE(HDMITX_Aud_CHS… in hdmi_tx_init()
1502 …it6161_hdmi_tx_write_table(it6161, HDMITX_AUD_SPDIF_2ch_24bit, ARRAY_SIZE(HDMITX_AUD_SPDIF_2ch_24b… in hdmi_tx_init()
1505 it6161_hdmi_tx_change_bank(it6161, 0); in hdmi_tx_init()
1506 … it6161_hdmi_tx_set_bits(it6161, 0x8D, 0x01, 0x01);//it6161_hdmi_tx_write(it6161, 0xf, 0 ); //pet in hdmi_tx_init()
1513 static bool mipi_rx_get_m_video_stable(struct it6161 *it6161) in mipi_rx_get_m_video_stable() argument
1515 return !!(it6161_mipi_rx_read(it6161, 0x0D) & 0x10); in mipi_rx_get_m_video_stable()
1518 static bool mipi_rx_get_p_video_stable(struct it6161 *it6161) in mipi_rx_get_p_video_stable() argument
1520 return !!(it6161_mipi_rx_read(it6161, 0x0D) & 0x20); in mipi_rx_get_p_video_stable()
1523 static void mipi_rx_setup_polarity(struct it6161 *it6161) in mipi_rx_setup_polarity() argument
1525 struct drm_display_mode *display_mode = &it6161->source_display_mode; in mipi_rx_setup_polarity()
1531 it6161_mipi_rx_set_bits(it6161, 0x4E, 0x03, polarity); in mipi_rx_setup_polarity()
1534 static void mipi_rx_afe_configuration(struct it6161 *it6161, u8 data_id) in mipi_rx_afe_configuration() argument
1537 u8 MPLaneNum = (it6161->mipi_rx_lane_count - 1); in mipi_rx_afe_configuration()
1544 … it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x02); // MPPCLKSel = 1; // 4-lane : MCLK = 1/1 PCLK in mipi_rx_afe_configuration()
1553 … it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x05); // MPPCLKSel = 6; // 2-lane : MCLK = 1/1 PCLK in mipi_rx_afe_configuration()
1564 … it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x08); // MPPCLKSel = 8; // 1-lane : MCLK = 3/4 PCLK in mipi_rx_afe_configuration()
1571 … it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x02);// MPPCLKSel = 1; // 4-lane : MCLK = 3/4 PCLK in mipi_rx_afe_configuration()
1576 … it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x05); // MPPCLKSel = 3; // 2-lane : MCLK = 3/4 PCLK in mipi_rx_afe_configuration()
1581 … it6161_mipi_rx_set_bits(it6161, 0x80, 0x1F, 0x0b); // MPPCLKSel = 5; // 1-lane : MCLK = 3/4 PCLK in mipi_rx_afe_configuration()
1586 static void mipi_rx_configuration(struct it6161 *it6161) in mipi_rx_configuration() argument
1589 u8 mipi_lane_config = (it6161->mipi_rx_lane_count - 1); in mipi_rx_configuration()
1592 it6161_mipi_rx_set_bits(it6161, 0x10, 0x0F, 0x0F); in mipi_rx_configuration()
1594 it6161_mipi_rx_set_bits(it6161, 0x10, 0x0F, 0x00); in mipi_rx_configuration()
1600 mipi_rx_logic_reset(it6161); in mipi_rx_configuration()
1602 mipi_rx_logic_reset_release(it6161); in mipi_rx_configuration()
1604 it6161_mipi_rx_int_mask_disable(it6161); in mipi_rx_configuration()
1607 it6161_mipi_rx_set_bits(it6161, 0x0d, 0x02, 0x00); in mipi_rx_configuration()
1609 it6161_mipi_rx_set_bits(it6161, 0x0C, 0x0F, (MPLaneSwap<<3) + (MPPNSwap<<2) + mipi_lane_config); in mipi_rx_configuration()
1611 …it6161_mipi_rx_set_bits(it6161, 0x11, 0x3F, (EnIOIDDQ<<5)+(EnStb2Rst<<4)+(EnExtStdby<<3)+(EnStandb… in mipi_rx_configuration()
1612 it6161_mipi_rx_set_bits(it6161, 0x12, 0x03, (PDREFCNT<<1)+PDREFCLK); in mipi_rx_configuration()
1614 it6161_mipi_rx_set_bits(it6161, 0x18, 0xf7, (RegEnSyncErr<<7)+(SkipStg<<4)+HSSetNum); in mipi_rx_configuration()
1615 it6161_mipi_rx_set_bits(it6161, 0x19, 0xf3, (PPIDbgSel<<4)+(EnContCK<<1)+EnDeSkew); in mipi_rx_configuration()
1616 …it6161_mipi_rx_set_bits(it6161, 0x20, 0xf7, (EOTPSel<<4)+(RegEnDummyECC<<2)+(RegIgnrBlk<<1)+RegIgn… in mipi_rx_configuration()
1617 it6161_mipi_rx_set_bits(it6161, 0x21, 0x07, LMDbgSel); in mipi_rx_configuration()
1620 …it6161_mipi_rx_set_bits(it6161, 0x44, 0x3a, (MREC_Update<<5)+(PREC_Update<<4)+(REGSELDEF<<3)+(RegA… in mipi_rx_configuration()
1621 it6161_mipi_rx_set_bits(it6161, 0x4B, 0x1f, (EnFReSync<<4)+(EnVREnh<<3)+EnVREnhSel); in mipi_rx_configuration()
1622 it6161_mipi_rx_write(it6161, 0x4C, PPSFFRdStg); in mipi_rx_configuration()
1623 it6161_mipi_rx_set_bits(it6161, 0x4D, 0x01, (PPSFFRdStg>>8)&0x01); in mipi_rx_configuration()
1624 it6161_mipi_rx_set_bits(it6161, 0x4E, 0x0C, (EnVReSync<<3)+(EnHReSync<<2)); in mipi_rx_configuration()
1625 it6161_mipi_rx_set_bits(it6161, 0x4F, 0x03, EnFFAutoRst); in mipi_rx_configuration()
1628 it6161_mipi_rx_set_bits(it6161, 0x70, 0x01, EnMAvg); in mipi_rx_configuration()
1629 it6161_mipi_rx_write(it6161, 0x72, MShift); in mipi_rx_configuration()
1630 it6161_mipi_rx_write(it6161, 0x73, PShift); in mipi_rx_configuration()
1631 it6161_mipi_rx_set_bits(it6161, 0x80, 0x20, ENABLE_MIPI_RX_EXTERNAL_CLOCK << 5); in mipi_rx_configuration()
1632 it6161_mipi_rx_write(it6161, 0x21, 0x00); //debug sel in mipi_rx_configuration()
1635 it6161_mipi_rx_set_bits(it6161, 0x84, 0x70, 0x00); // min swing in mipi_rx_configuration()
1637 it6161_mipi_rx_set_bits(it6161, 0xA0, 0x01, EnMBPM); in mipi_rx_configuration()
1640 it6161_mipi_rx_set_bits(it6161, 0x21, 0x08, 0x08); in mipi_rx_configuration()
1657 it6161_mipi_rx_set_bits(it6161, 0x70, 0x01, EnMAvg); in mipi_rx_configuration()
1659 it6161_mipi_rx_set_bits(it6161, 0x05, 0x02, 0x02); // Video Clock Domain Reset in mipi_rx_configuration()
1665 it6161_mipi_rx_write(it6161, 0xA1, 0x00); // HRS offset in mipi_rx_configuration()
1666 it6161_mipi_rx_write(it6161, 0xA2, 0x00); // VRS offset in mipi_rx_configuration()
1670 it6161_mipi_rx_write(it6161, 0xA3, 0x08);//0x10); // HSW in mipi_rx_configuration()
1671 it6161_mipi_rx_write(it6161, 0xA5, 0x04); // VSw in mipi_rx_configuration()
1704 it6161_mipi_rx_set_bits(it6161, 0x31, 0x80, 0x00); in mipi_rx_configuration()
1705 it6161_mipi_rx_set_bits(it6161, 0x33, 0x80, 0x00); in mipi_rx_configuration()
1706 it6161_mipi_rx_set_bits(it6161, 0x35, 0x80, 0x00); in mipi_rx_configuration()
1707 it6161_mipi_rx_set_bits(it6161, 0x37, 0x80, 0x00); in mipi_rx_configuration()
1708 it6161_mipi_rx_set_bits(it6161, 0x39, 0x80, 0x00); in mipi_rx_configuration()
1709 it6161_mipi_rx_set_bits(it6161, 0x3A, 0x80, 0x00); in mipi_rx_configuration()
1710 it6161_mipi_rx_set_bits(it6161, 0x3C, 0x80, 0x00); in mipi_rx_configuration()
1711 it6161_mipi_rx_set_bits(it6161, 0x3E, 0x80, 0x00); in mipi_rx_configuration()
1712 it6161_mipi_rx_set_bits(it6161, 0x41, 0x80, 0x00); in mipi_rx_configuration()
1713 it6161_mipi_rx_set_bits(it6161, 0x43, 0x80, 0x00); in mipi_rx_configuration()
1720 static void mipi_rx_init(struct it6161 *it6161) in mipi_rx_init() argument
1725 mipi_rx_configuration(it6161); in mipi_rx_init()
1726 it6161_mipi_rx_set_bits(it6161, 0x05, 0x03, 0x00); // Enable MPRX clock domain in mipi_rx_init()
1729 static void hdmi_tx_video_reset(struct it6161 *it6161) in hdmi_tx_video_reset() argument
1733 …it6161, 0x04), it6161_hdmi_tx_read(it6161, 0x05), it6161_hdmi_tx_read(it6161, 0x06), it6161_hdmi_t… in hdmi_tx_video_reset()
1734 it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_HDMITX_VID_RST, B_HDMITX_VID_RST); in hdmi_tx_video_reset()
1735 it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_HDMITX_VID_RST, 0x00); in hdmi_tx_video_reset()
1747 static void it6161_hdmi_tx_clear_ddc_fifo(struct it6161 *it6161) in it6161_hdmi_tx_clear_ddc_fifo() argument
1749 it6161_hdmi_tx_change_bank(it6161, 0); in it6161_hdmi_tx_clear_ddc_fifo()
1750 it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERDDC | B_TX_MASTERHOST); in it6161_hdmi_tx_clear_ddc_fifo()
1751 it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD, CMD_FIFO_CLR); in it6161_hdmi_tx_clear_ddc_fifo()
1752 it6161_hdmi_tx_set_bits(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERHOST, 0x00); in it6161_hdmi_tx_clear_ddc_fifo()
1756 static void it6161_hdmi_tx_generate_ddc_sclk(struct it6161 *it6161) in it6161_hdmi_tx_generate_ddc_sclk() argument
1758 it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL,B_TX_MASTERDDC|B_TX_MASTERHOST); in it6161_hdmi_tx_generate_ddc_sclk()
1759 it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD,CMD_GEN_SCLCLK); in it6161_hdmi_tx_generate_ddc_sclk()
1762 static void hdmi_tx_generate_blank_timing(struct it6161 *it6161) in hdmi_tx_generate_blank_timing() argument
1764 struct drm_display_mode *display_mode = &it6161->source_display_mode; in hdmi_tx_generate_blank_timing()
1779 …it6161_hdmi_tx_set_bits(it6161, 0xD1, 0x0C, force_hdmi_tx_clock_stable << 3 | force_hdmi_tx_video_… in hdmi_tx_generate_blank_timing()
1780 it6161_hdmi_tx_set_bits(it6161, 0xA9, 0x80, hdmi_tx_by_pass_mode << 7); in hdmi_tx_generate_blank_timing()
1781 it6161_hdmi_tx_set_bits(it6161, 0x90, 0x01, de_generation); in hdmi_tx_generate_blank_timing()
1782 it6161_hdmi_tx_write(it6161, 0x91, vsync_rising_at_h_2nd >> 4); in hdmi_tx_generate_blank_timing()
1783 it6161_hdmi_tx_set_bits(it6161, 0x90, 0xF0, (vsync_rising_at_h_2nd & 0x00F) << 4); in hdmi_tx_generate_blank_timing()
1784 it6161_hdmi_tx_set_bits(it6161, 0x90, 0x06, polarity); in hdmi_tx_generate_blank_timing()
1785 it6161_hdmi_tx_write(it6161, 0x95, (u8)hsync_start); in hdmi_tx_generate_blank_timing()
1786 it6161_hdmi_tx_write(it6161, 0x96, (u8)hsync_end); in hdmi_tx_generate_blank_timing()
1787 it6161_hdmi_tx_write(it6161, 0x97, (hsync_end & 0x0F00) >> 4 | hsync_start >> 8); in hdmi_tx_generate_blank_timing()
1796 it6161_hdmi_tx_set_bits(it6161, 0xA5, 0x10, 0x00); in hdmi_tx_generate_blank_timing()
1799 it6161_hdmi_tx_set_bits(it6161, 0xA5, 0x10, 0x10); in hdmi_tx_generate_blank_timing()
1801 it6161_hdmi_tx_write(it6161, 0xA0, (u8)vsync_start); in hdmi_tx_generate_blank_timing()
1802 it6161_hdmi_tx_write(it6161, 0xA1, (vsync_end & 0x0F) << 4 | vsync_start >> 8); in hdmi_tx_generate_blank_timing()
1803 it6161_hdmi_tx_write(it6161, 0xA2, (u8)vsync_start_2nd); in hdmi_tx_generate_blank_timing()
1804 it6161_hdmi_tx_write(it6161, 0xA6, (vsync_end_2nd & 0xF0) | vsync_end >> 4); in hdmi_tx_generate_blank_timing()
1805 it6161_hdmi_tx_write(it6161, 0xA3, (vsync_end_2nd & 0x0F) << 4 | vsync_start_2nd >> 8); in hdmi_tx_generate_blank_timing()
1806 it6161_hdmi_tx_write(it6161, 0xA4, vsync_rising_at_h_2nd); in hdmi_tx_generate_blank_timing()
1807 …it6161_hdmi_tx_set_bits(it6161, 0xB1, 0x51, (hsync_end & 0x1000) >> 6 | (hsync_start & 0x1000) >> … in hdmi_tx_generate_blank_timing()
1808 it6161_hdmi_tx_set_bits(it6161, 0xA5, 0x2F, enable_de_only << 5 | vsync_rising_at_h_2nd >> 8); in hdmi_tx_generate_blank_timing()
1809 …it6161_hdmi_tx_set_bits(it6161, 0xB2, 0x05, (vsync_rising_at_h_2nd & 0x1000) >> 10 | (vsync_rising… in hdmi_tx_generate_blank_timing()
1812 it6161_hdmi_tx_set_bits(it6161, 0x90, 0xF0, (htotal & 0x0F) << 4); in hdmi_tx_generate_blank_timing()
1813 it6161_hdmi_tx_write(it6161, 0x91, (htotal & 0x0FF0) >> 4); in hdmi_tx_generate_blank_timing()
1814 it6161_hdmi_tx_set_bits(it6161, 0xB2, 0x01, (htotal & 0x1000) >> 12); in hdmi_tx_generate_blank_timing()
1815 it6161_hdmi_tx_write(it6161, 0x98, vtotal & 0x0FF); in hdmi_tx_generate_blank_timing()
1816 it6161_hdmi_tx_write(it6161, 0x99, (vtotal & 0xF00) >> 8); in hdmi_tx_generate_blank_timing()
1821 static void it6161_hdmi_tx_abort_ddc(struct it6161 *it6161) in it6161_hdmi_tx_abort_ddc() argument
1828 sw_reset = it6161_hdmi_tx_read(it6161, REG_TX_SW_RST); in it6161_hdmi_tx_abort_ddc()
1829 cp_desire = it6161_hdmi_tx_read(it6161, REG_TX_HDCP_DESIRE); in it6161_hdmi_tx_abort_ddc()
1830 ddc_master = it6161_hdmi_tx_read(it6161, REG_TX_DDC_MASTER_CTRL); in it6161_hdmi_tx_abort_ddc()
1833 …it6161_hdmi_tx_write(it6161, REG_TX_SW_RST, sw_reset | B_TX_HDCP_RST_HDMITX); // @emily ch… in it6161_hdmi_tx_abort_ddc()
1834 it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERDDC | B_TX_MASTERHOST); in it6161_hdmi_tx_abort_ddc()
1838 it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD, CMD_DDC_ABORT); in it6161_hdmi_tx_abort_ddc()
1839 …it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD, CMD_GEN_SCLCLK);//hdmitxwr(0x15, 0x0A); //it6161A0 … in it6161_hdmi_tx_abort_ddc()
1842 uc = it6161_hdmi_tx_read(it6161, REG_TX_DDC_STATUS); in it6161_hdmi_tx_abort_ddc()
1856 static bool hdmi_tx_get_video_state(struct it6161 *it6161) in hdmi_tx_get_video_state() argument
1858 return !!(B_TXVIDSTABLE & it6161_hdmi_tx_read(it6161, REG_TX_SYS_STATUS)); in hdmi_tx_get_video_state()
1861 static bool inline hdmi_tx_get_sink_hpd(struct it6161 *it6161) in hdmi_tx_get_sink_hpd() argument
1863 return !!(it6161_hdmi_tx_read(it6161, REG_TX_SYS_STATUS) & B_TX_HPDETECT); in hdmi_tx_get_sink_hpd()
1866 static bool it6161_ddc_op_finished(struct it6161 *it6161) in it6161_ddc_op_finished() argument
1868 int reg16 = it6161_hdmi_tx_read(it6161, REG_TX_DDC_STATUS); in it6161_ddc_op_finished()
1876 static int it6161_ddc_wait(struct it6161 *it6161) in it6161_ddc_wait() argument
1884 while (!it6161_ddc_op_finished(it6161)) { in it6161_ddc_wait()
1892 status = it6161_hdmi_tx_read(it6161, REG_TX_DDC_STATUS); in it6161_ddc_wait()
1906 static void hdmi_tx_ddc_operation(struct it6161 *it6161, u8 addr, u8 offset, u8 size, u8 segment, u… in hdmi_tx_ddc_operation() argument
1909 it6161_hdmi_tx_change_bank(it6161, 0); in hdmi_tx_ddc_operation()
1910 it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERDDC | B_TX_MASTERHOST); in hdmi_tx_ddc_operation()
1911 it6161_hdmi_tx_write(it6161, REG_TX_DDC_HEADER, addr); in hdmi_tx_ddc_operation()
1912 it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQOFF, offset); in hdmi_tx_ddc_operation()
1913 it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQCOUNT, size); in hdmi_tx_ddc_operation()
1914 it6161_hdmi_tx_write(it6161, REG_TX_DDC_EDIDSEG, segment); in hdmi_tx_ddc_operation()
1915 it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD, cmd); in hdmi_tx_ddc_operation()
1929 static int it6161_ddc_get_edid_operation(struct it6161 *it6161, u8 *buffer, u8 segment, u8 offset, … in it6161_ddc_get_edid_operation() argument
1936 if(it6161_hdmi_tx_read(it6161, REG_TX_INT_STAT1) & B_TX_INT_DDC_BUS_HANG) { in it6161_ddc_get_edid_operation()
1938 it6161_hdmi_tx_abort_ddc(it6161); in it6161_ddc_get_edid_operation()
1941 it6161_hdmi_tx_clear_ddc_fifo(it6161); in it6161_ddc_get_edid_operation()
1942 status = it6161_ddc_wait(it6161); in it6161_ddc_get_edid_operation()
1947 hdmi_tx_ddc_operation(it6161, DDC_EDID_ADDRESS, offset, size, segment, CMD_EDID_READ); in it6161_ddc_get_edid_operation()
1948 status = it6161_ddc_wait(it6161); in it6161_ddc_get_edid_operation()
1954 status = it6161_hdmi_tx_read(it6161, REG_TX_DDC_READFIFO); in it6161_ddc_get_edid_operation()
1971 struct it6161 *it6161 = data; in it6161_get_edid_block() local
1978 …ret = it6161_ddc_get_edid_operation(it6161, buf + offset, block_num / 2, (block_num % 2) * EDID_LE… in it6161_get_edid_block()
1995 static void hdmi_tx_set_capability_from_edid_parse(struct it6161 *it6161) in hdmi_tx_set_capability_from_edid_parse() argument
1997 struct drm_display_info *info = &it6161->connector.display_info; in hdmi_tx_set_capability_from_edid_parse()
1999 it6161->hdmi_mode = drm_detect_hdmi_monitor(it6161->edid); in hdmi_tx_set_capability_from_edid_parse()
2000 it6161->support_audio = drm_detect_monitor_audio(it6161->edid); in hdmi_tx_set_capability_from_edid_parse()
2001 if (it6161->hdmi_tx_output_color_space == F_MODE_YUV444) { in hdmi_tx_set_capability_from_edid_parse()
2003 it6161->hdmi_tx_output_color_space &= ~F_MODE_CLRMOD_MASK; in hdmi_tx_set_capability_from_edid_parse()
2004 it6161->hdmi_tx_output_color_space |= F_MODE_RGB444; in hdmi_tx_set_capability_from_edid_parse()
2008 if (it6161->hdmi_tx_output_color_space == F_MODE_YUV422) { in hdmi_tx_set_capability_from_edid_parse()
2010 it6161->hdmi_tx_output_color_space &= ~F_MODE_CLRMOD_MASK; in hdmi_tx_set_capability_from_edid_parse()
2011 it6161->hdmi_tx_output_color_space |= F_MODE_RGB444; in hdmi_tx_set_capability_from_edid_parse()
2015 …it6161->hdmi_mode ? "HDMI" : "DVI", it6161->support_audio ? "" : "not ", it6161->hdmi_tx_output_co… in hdmi_tx_set_capability_from_edid_parse()
2025 static void it6161_variable_config(struct it6161 *it6161) in it6161_variable_config() argument
2027 it6161->hdmi_tx_hdcp_retry = HDMI_TX_HDCP_RETRY; in it6161_variable_config()
2028 it6161->hdmi_tx_mode = HDMI_TX_MODE; in it6161_variable_config()
2029 it6161->mipi_rx_lane_count = MIPI_RX_LANE_COUNT; in it6161_variable_config()
2036 struct it6161 *it6161 = connector_to_it6161(connector); in it6161_get_modes() local
2038 struct device *dev = &it6161->i2c_mipi_rx->dev; in it6161_get_modes()
2042 if (it6161->edid) in it6161_get_modes()
2043 return drm_add_edid_modes(connector, it6161->edid); in it6161_get_modes()
2044 mutex_lock(&it6161->mode_lock); in it6161_get_modes()
2045 reinit_completion(&it6161->wait_edid_complete); in it6161_get_modes()
2048 it6161->edid = in it6161_get_modes()
2049 drm_do_get_edid(&it6161->connector, it6161_get_edid_block, it6161); in it6161_get_modes()
2051 if (it6161->edid) in it6161_get_modes()
2054 if (!it6161->edid) { in it6161_get_modes()
2059 err = drm_connector_update_edid_property(connector, it6161->edid); in it6161_get_modes()
2065 num_modes = drm_add_edid_modes(connector, it6161->edid); in it6161_get_modes()
2068 complete(&it6161->wait_edid_complete); in it6161_get_modes()
2070 mutex_unlock(&it6161->mode_lock); in it6161_get_modes()
2082 struct it6161 *it6161 = connector_to_it6161(connector); in it6161_detect() local
2084 bool hpd = hdmi_tx_get_sink_hpd(it6161); in it6161_detect()
2090 it6161_variable_config(it6161); in it6161_detect()
2095 it6161_mipi_rx_int_mask_enable(it6161); in it6161_detect()
2096 it6161_hdmi_tx_int_mask_enable(it6161); in it6161_detect()
2111 static int it6161_attach_dsi(struct it6161 *it6161) in it6161_attach_dsi() argument
2119 host = of_find_mipi_dsi_host_by_node(it6161->host_node); in it6161_attach_dsi()
2132 it6161->dsi = dsi; in it6161_attach_dsi()
2156 struct it6161 *it6161 = bridge_to_it6161(bridge); in it6161_bridge_attach() local
2160 dev = &it6161->i2c_mipi_rx->dev; in it6161_bridge_attach()
2166 err = drm_connector_init(bridge->dev, &it6161->connector, in it6161_bridge_attach()
2174 drm_connector_helper_add(&it6161->connector, in it6161_bridge_attach()
2177 it6161->connector.polled = DRM_CONNECTOR_POLL_HPD; in it6161_bridge_attach()
2179 err = drm_connector_attach_encoder(&it6161->connector, bridge->encoder); in it6161_bridge_attach()
2186 DRM_INFO("%s, ret:%d", __func__, it6161_attach_dsi(it6161)); in it6161_bridge_attach()
2188 err = drm_connector_register(&it6161->connector); in it6161_bridge_attach()
2200 drm_connector_cleanup(&it6161->connector); in it6161_bridge_attach()
2204 static void it6161_detach_dsi(struct it6161 *it6161) in it6161_detach_dsi() argument
2206 mipi_dsi_detach(it6161->dsi); in it6161_detach_dsi()
2207 mipi_dsi_device_unregister(it6161->dsi); in it6161_detach_dsi()
2212 struct it6161 *it6161 = bridge_to_it6161(bridge); in it6161_bridge_detach() local
2214 drm_connector_unregister(&it6161->connector); in it6161_bridge_detach()
2215 drm_connector_cleanup(&it6161->connector); in it6161_bridge_detach()
2216 it6161_detach_dsi(it6161); in it6161_bridge_detach()
2278 struct it6161 *it6161 = bridge_to_it6161(bridge); in it6161_bridge_mode_set() local
2279 struct device *dev = &it6161->i2c_mipi_rx->dev; in it6161_bridge_mode_set()
2280 struct drm_display_mode *display_mode = &it6161->source_display_mode; in it6161_bridge_mode_set()
2283 mutex_lock(&it6161->mode_lock); in it6161_bridge_mode_set()
2284 err = drm_hdmi_avi_infoframe_from_display_mode(&it6161->source_avi_infoframe, &it6161->connector, in it6161_bridge_mode_set()
2292 strlcpy(it6161->hdmi_tx_display_mode.name, adjusted_mode->name, in it6161_bridge_mode_set()
2294 it6161->hdmi_tx_display_mode.type = adjusted_mode->type; in it6161_bridge_mode_set()
2295 it6161->hdmi_tx_display_mode.flags = adjusted_mode->flags; in it6161_bridge_mode_set()
2309 it6161->vic = it6161->source_avi_infoframe.video_code; in it6161_bridge_mode_set()
2324 mutex_unlock(&it6161->mode_lock); in it6161_bridge_mode_set()
2329 struct it6161 *it6161 = bridge_to_it6161(bridge); in it6161_bridge_enable() local
2333 mipi_rx_init(it6161);//allen in it6161_bridge_enable()
2334 hdmi_tx_init(it6161);//allen in it6161_bridge_enable()
2336 it6161_mipi_rx_int_mask_enable(it6161); in it6161_bridge_enable()
2337 it6161_hdmi_tx_int_mask_enable(it6161); in it6161_bridge_enable()
2340 schedule_delayed_work(&it6161->restart, msecs_to_jiffies(2000)); in it6161_bridge_enable()
2354 struct it6161 *it6161 = bridge_to_it6161(bridge); in it6161_bridge_disable() local
2357 mipi_rx_logic_reset(it6161); in it6161_bridge_disable()
2358 hdmi_tx_logic_reset(it6161); in it6161_bridge_disable()
2360 it6161_mipi_rx_int_mask_enable(it6161); in it6161_bridge_disable()
2361 it6161_hdmi_tx_int_mask_enable(it6161);//--- in it6161_bridge_disable()
2377 #define InitCEC() it6161_hdmi_tx_write(it6161, 0x8D, (CEC_I2C_SLAVE_ADDR|0x01))//HDMITX_SetI2C_Byte…
2378 #define DisableCEC() it6161_hdmi_tx_set_bits(it6161, 0x8D, 0x01, 0x00)//HDMITX_SetI2C_Byte(0x0F, 0x…
2380 static bool it6161_check_device_ready(struct it6161 *it6161) in it6161_check_device_ready() argument
2384 Vendor_ID[0] = it6161_mipi_rx_read(it6161, 0x00); in it6161_check_device_ready()
2385 Vendor_ID[1] = it6161_mipi_rx_read(it6161, 0x01); in it6161_check_device_ready()
2386 Device_ID[0] = it6161_mipi_rx_read(it6161, 0x02); in it6161_check_device_ready()
2387 Device_ID[1] = it6161_mipi_rx_read(it6161, 0x03); in it6161_check_device_ready()
2391 DRM_INFO("Find 6161 revision: 0x%2x", (u32)it6161_mipi_rx_read(it6161, 0x04)); in it6161_check_device_ready()
2398 static u32 hdmi_tx_calc_rclk(struct it6161 *it6161)//in c code: cal_txrclk in hdmi_tx_calc_rclk() argument
2410 it6161_cec_write(it6161, 0x09, 1); in hdmi_tx_calc_rclk()
2412 it6161_cec_write(it6161, 0x09, 0); in hdmi_tx_calc_rclk()
2413 RCLKCNT = it6161_cec_read(it6161, 0x47); in hdmi_tx_calc_rclk()
2415 RCLKCNT |= it6161_cec_read(it6161, 0x46); in hdmi_tx_calc_rclk()
2417 RCLKCNT |= it6161_cec_read(it6161, 0x45); in hdmi_tx_calc_rclk()
2423 it6161_cec_write(it6161, 0x0C, (RCLKCNT & 0xFF)); in hdmi_tx_calc_rclk()
2428 it6161->hdmi_tx_rclk = (sum << 4) / 104;//actually nxp platform msleep(100) is 108ms in hdmi_tx_calc_rclk()
2429 DRM_INFO("hdmi tx rclk = %d.%dMHz", it6161->hdmi_tx_rclk / 1000, it6161->hdmi_tx_rclk % 1000); in hdmi_tx_calc_rclk()
2438 it6161_hdmi_tx_write(it6161, 0x47, (TimeLoMax&0xFF)); in hdmi_tx_calc_rclk()
2439 it6161_hdmi_tx_write(it6161, 0x48, ((TimeLoMax&0xFF00)>>8)); in hdmi_tx_calc_rclk()
2440 it6161_hdmi_tx_set_bits(it6161, 0x49, 0x03, ((TimeLoMax&0x30000)>>16)); in hdmi_tx_calc_rclk()
2442 return it6161->hdmi_tx_rclk; in hdmi_tx_calc_rclk()
2445 static u32 hdmi_tx_calc_pclk(struct it6161 *it6161) //c code void cal_txclk( void ) in hdmi_tx_calc_pclk() argument
2451 it6161_hdmi_tx_change_bank(it6161, 0); in hdmi_tx_calc_pclk()
2458 …RCLKFreqSelRead = (it6161_hdmi_tx_read(it6161, 0x5D) & 0x04)>>2;//hdmitxset(0x5D, 0x04, (RCLKFreqS… in hdmi_tx_calc_pclk()
2460 it6161_hdmi_tx_set_bits(it6161, 0xD7, 0xF0, 0x80); in hdmi_tx_calc_pclk()
2462 it6161_hdmi_tx_set_bits(it6161, 0xD7, 0x80, 0x00); in hdmi_tx_calc_pclk()
2464 count = it6161_hdmi_tx_read(it6161, 0xD7) & 0xF ; in hdmi_tx_calc_pclk()
2466 count |= it6161_hdmi_tx_read(it6161, 0xD8); in hdmi_tx_calc_pclk()
2481 it6161_hdmi_tx_set_bits(it6161, 0xD7, 0x70, div<<4); in hdmi_tx_calc_pclk()
2483 uc = it6161_hdmi_tx_read(it6161, 0xD7) & 0x7F ; in hdmi_tx_calc_pclk()
2486 it6161_hdmi_tx_write(it6161, 0xD7, uc|0x80) ; in hdmi_tx_calc_pclk()
2488 it6161_hdmi_tx_write(it6161, 0xD7, uc) ; in hdmi_tx_calc_pclk()
2490 count = it6161_hdmi_tx_read(it6161, 0xD7) & 0xF ; in hdmi_tx_calc_pclk()
2492 count |= it6161_hdmi_tx_read(it6161, 0xD8); in hdmi_tx_calc_pclk()
2502 it6161->hdmi_tx_pclk = it6161->hdmi_tx_rclk * 128 / count * 16 ;//128*16=2048 in hdmi_tx_calc_pclk()
2503 it6161->hdmi_tx_pclk *= (1<<div); in hdmi_tx_calc_pclk()
2510 DRM_INFO("hdmi tx pclk = %d.%dMHz", it6161->hdmi_tx_pclk / 1000, it6161->hdmi_tx_pclk % 1000); in hdmi_tx_calc_pclk()
2511 return it6161->hdmi_tx_pclk; in hdmi_tx_calc_pclk()
2514 static void hdmi_tx_get_display_mode(struct it6161 *it6161) in hdmi_tx_get_display_mode() argument
2516 struct drm_display_mode *display_mode = &it6161->hdmi_tx_display_mode; in hdmi_tx_get_display_mode()
2523 hdmi_tx_calc_rclk(it6161); in hdmi_tx_get_display_mode()
2524 hdmi_tx_calc_pclk(it6161); in hdmi_tx_get_display_mode()
2527 it6161_hdmi_tx_set_bits(it6161, 0xA8, 0x08, 0x08); in hdmi_tx_get_display_mode()
2529 rega9 = it6161_hdmi_tx_read(it6161, 0xa9); in hdmi_tx_get_display_mode()
2535 htotal = hdmi_tx_read_word(it6161, 0x98) & 0x0FFF; in hdmi_tx_get_display_mode()
2536 hdes = hdmi_tx_read_word(it6161, 0x90) & 0x0FFF; in hdmi_tx_get_display_mode()
2537 hdee = hdmi_tx_read_word(it6161, 0x92) & 0x0FFF; in hdmi_tx_get_display_mode()
2538 hsyncw = hdmi_tx_read_word(it6161, 0x94) & 0x0FFF; in hdmi_tx_get_display_mode()
2542 vtotal = hdmi_tx_read_word(it6161, 0xA6) & 0x0FFF; in hdmi_tx_get_display_mode()
2543 vdes = hdmi_tx_read_word(it6161, 0x9C) & 0x0FFF; in hdmi_tx_get_display_mode()
2544 vdee = hdmi_tx_read_word(it6161, 0x9E) & 0x0FFF; in hdmi_tx_get_display_mode()
2545 vsyncw = it6161_hdmi_tx_read(it6161, 0xA0); in hdmi_tx_get_display_mode()
2549 display_mode->clock = it6161->hdmi_tx_pclk; in hdmi_tx_get_display_mode()
2563 vdes2nd = hdmi_tx_read_word(it6161, 0xA2) & 0x0FFF; in hdmi_tx_get_display_mode()
2564 vdee2nd = hdmi_tx_read_word(it6161, 0xA4) & 0x0FFF; in hdmi_tx_get_display_mode()
2565 VRS2nd = hdmi_tx_read_word(it6161, 0xB1) & 0x0FFF; in hdmi_tx_get_display_mode()
2566 vsyncw2nd = it6161_hdmi_tx_read(it6161, 0xA1); in hdmi_tx_get_display_mode()
2567 H2ndVRRise = hdmi_tx_read_word(it6161, 0x96) & 0x0FFF; in hdmi_tx_get_display_mode()
2579 it6161_hdmi_tx_set_bits(it6161, 0xA8, 0x08, 0x00); in hdmi_tx_get_display_mode()
2582 static void it6161_hdmi_tx_set_av_mute(struct it6161 *it6161, u8 bEnable) in it6161_hdmi_tx_set_av_mute() argument
2584 it6161_hdmi_tx_change_bank(it6161, 0); in it6161_hdmi_tx_set_av_mute()
2585 it6161_hdmi_tx_set_bits(it6161, REG_TX_GCP,B_TX_SETAVMUTE, bEnable?B_TX_SETAVMUTE:0 ); in it6161_hdmi_tx_set_av_mute()
2586 it6161_hdmi_tx_write(it6161, REG_TX_PKT_GENERAL_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); in it6161_hdmi_tx_set_av_mute()
2598 static bool hdmi_tx_hdcp_auth_status(struct it6161 *it6161) in hdmi_tx_hdcp_auth_status() argument
2600 return !!(it6161_hdmi_tx_read(it6161, REG_TX_AUTH_STAT) & B_TX_AUTH_DONE); in hdmi_tx_hdcp_auth_status()
2603 static bool hdmi_tx_hdcp_get_auth_done(struct it6161 *it6161) in hdmi_tx_hdcp_get_auth_done() argument
2608 static void hdmi_tx_hdcp_clear_auth_interrupt(struct it6161 *it6161) in hdmi_tx_hdcp_clear_auth_interrupt() argument
2610 …it6161_hdmi_tx_set_bits(it6161, REG_TX_INT_MASK2, B_TX_KSVLISTCHK_MASK | B_TX_AUTH_DONE_MASK | B_T… in hdmi_tx_hdcp_clear_auth_interrupt()
2611 …it6161_hdmi_tx_write(it6161, REG_TX_INT_CLR0, B_TX_CLR_AUTH_FAIL | B_TX_CLR_AUTH_DONE | B_TX_CLR_K… in hdmi_tx_hdcp_clear_auth_interrupt()
2612 it6161_hdmi_tx_write(it6161, REG_TX_INT_CLR1, 0x00); in hdmi_tx_hdcp_clear_auth_interrupt()
2613 it6161_hdmi_tx_write(it6161, REG_TX_SYS_STATUS, B_TX_INTACTDONE); in hdmi_tx_hdcp_clear_auth_interrupt()
2616 static void hdmi_tx_hdcp_reset_auth(struct it6161 *it6161) in hdmi_tx_hdcp_reset_auth() argument
2618 it6161_hdmi_tx_write(it6161, REG_TX_LISTCTRL, 0x00); in hdmi_tx_hdcp_reset_auth()
2619 it6161_hdmi_tx_write(it6161, REG_TX_HDCP_DESIRE, 0x00); in hdmi_tx_hdcp_reset_auth()
2620 it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_TX_HDCP_RST_HDMITX, B_TX_HDCP_RST_HDMITX); in hdmi_tx_hdcp_reset_auth()
2621 it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERDDC | B_TX_MASTERHOST); in hdmi_tx_hdcp_reset_auth()
2622 it6161_hdmi_tx_clear_ddc_fifo(it6161); in hdmi_tx_hdcp_reset_auth()
2623 it6161_hdmi_tx_abort_ddc(it6161); in hdmi_tx_hdcp_reset_auth()
2628 static void hdmi_tx_hdcp_auth_fire(struct it6161 *it6161) in hdmi_tx_hdcp_auth_fire() argument
2630 …it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERDDC | B_TX_MASTERHDCP); // MASTERH… in hdmi_tx_hdcp_auth_fire()
2631 it6161_hdmi_tx_write(it6161, REG_TX_AUTHFIRE, 0x01); in hdmi_tx_hdcp_auth_fire()
2639 static void hdmi_tx_hdcp_start_an_cipher(struct it6161 *it6161) in hdmi_tx_hdcp_start_an_cipher() argument
2641 it6161_hdmi_tx_write(it6161, REG_TX_AN_GENERATE, B_TX_START_CIPHER_GEN); in hdmi_tx_hdcp_start_an_cipher()
2646 static void hdmi_tx_hdcp_stop_an_cipher(struct it6161 *it6161) in hdmi_tx_hdcp_stop_an_cipher() argument
2648 it6161_hdmi_tx_write(it6161, REG_TX_AN_GENERATE, B_TX_STOP_CIPHER_GEN); in hdmi_tx_hdcp_stop_an_cipher()
2656 static void hdmi_tx_hdcp_generate_an(struct it6161 *it6161) in hdmi_tx_hdcp_generate_an() argument
2660 hdmi_tx_hdcp_start_an_cipher(it6161); in hdmi_tx_hdcp_generate_an()
2662 hdmi_tx_hdcp_stop_an_cipher(it6161); in hdmi_tx_hdcp_generate_an()
2663 it6161_hdmi_tx_change_bank(it6161, 0); in hdmi_tx_hdcp_generate_an()
2665 it6161_hdmi_tx_burst_read(it6161, REG_TX_AN_GEN, an, DRM_HDCP_AN_LEN); in hdmi_tx_hdcp_generate_an()
2668 it6161_hdmi_tx_write(it6161, REG_TX_AN + i, an[i]); in hdmi_tx_hdcp_generate_an()
2678 static SYS_STATUS hdmi_tx_get_hdcp_bcaps_bstatus(struct it6161 *it6161, u8 *pBCaps, u16 *pBStatus) in hdmi_tx_get_hdcp_bcaps_bstatus() argument
2682 it6161_hdmi_tx_change_bank(it6161, 0); in hdmi_tx_get_hdcp_bcaps_bstatus()
2683 it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL,B_TX_MASTERDDC|B_TX_MASTERHOST); in hdmi_tx_get_hdcp_bcaps_bstatus()
2684 it6161_hdmi_tx_write(it6161, REG_TX_DDC_HEADER,DDC_HDCP_ADDRESS); in hdmi_tx_get_hdcp_bcaps_bstatus()
2685 it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQOFF,0x40); // BCaps offset in hdmi_tx_get_hdcp_bcaps_bstatus()
2686 it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQCOUNT,3); in hdmi_tx_get_hdcp_bcaps_bstatus()
2687 it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD,CMD_DDC_SEQ_BURSTREAD); in hdmi_tx_get_hdcp_bcaps_bstatus()
2689 ucdata = it6161_ddc_wait(it6161); in hdmi_tx_get_hdcp_bcaps_bstatus()
2697 ucdata = it6161_hdmi_tx_read(it6161, REG_TX_BSTAT + 1); in hdmi_tx_get_hdcp_bcaps_bstatus()
2700 ucdata = it6161_hdmi_tx_read(it6161, REG_TX_BSTAT); in hdmi_tx_get_hdcp_bcaps_bstatus()
2702 *pBCaps = it6161_hdmi_tx_read(it6161, REG_TX_BCAP); in hdmi_tx_get_hdcp_bcaps_bstatus()
2704 *pBCaps = it6161_hdmi_tx_read(it6161, 0x17); in hdmi_tx_get_hdcp_bcaps_bstatus()
2705 *pBStatus = it6161_hdmi_tx_read(it6161, 0x17) & 0xFF ; in hdmi_tx_get_hdcp_bcaps_bstatus()
2706 *pBStatus |= (int)(it6161_hdmi_tx_read(it6161, 0x17)&0xFF)<<8; in hdmi_tx_get_hdcp_bcaps_bstatus()
2707 …DRM_INFO("hdmi_tx_get_hdcp_bcaps_bstatus(): ucdata = %02X\n",(int)it6161_hdmi_tx_read(it6161, 0x16… in hdmi_tx_get_hdcp_bcaps_bstatus()
2717 static int hdmi_tx_hdcp_get_bksv(struct it6161 *it6161, u8 *bksv, size_t size) in hdmi_tx_hdcp_get_bksv() argument
2724 …hdmi_tx_ddc_operation(it6161, DDC_HDCP_ADDRESS, DRM_HDCP_DDC_BKSV, size, 0x00, CMD_DDC_SEQ_BURSTRE… in hdmi_tx_hdcp_get_bksv()
2726 ret = it6161_ddc_wait(it6161); in hdmi_tx_hdcp_get_bksv()
2733 ret = it6161_hdmi_tx_burst_read(it6161, REG_TX_BKSV, bksv, size); in hdmi_tx_hdcp_get_bksv()
2758 static void hdmitx_hdcp_CancelRepeaterAuthenticate(struct it6161 *it6161) in hdmitx_hdcp_CancelRepeaterAuthenticate() argument
2761 it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERDDC | B_TX_MASTERHOST); in hdmitx_hdcp_CancelRepeaterAuthenticate()
2762 it6161_hdmi_tx_abort_ddc(it6161); in hdmitx_hdcp_CancelRepeaterAuthenticate()
2763 it6161_hdmi_tx_write(it6161, REG_TX_LISTCTRL, B_TX_LISTFAIL | B_TX_LISTDONE); in hdmitx_hdcp_CancelRepeaterAuthenticate()
2764 it6161_hdmi_tx_write(it6161, REG_TX_LISTCTRL, 0x00); in hdmitx_hdcp_CancelRepeaterAuthenticate()
2765 hdmi_tx_hdcp_clear_auth_interrupt(it6161); in hdmitx_hdcp_CancelRepeaterAuthenticate()
2768 static void hdmitx_hdcp_ResumeRepeaterAuthenticate(struct it6161 *it6161) in hdmitx_hdcp_ResumeRepeaterAuthenticate() argument
2770 it6161_hdmi_tx_write(it6161, REG_TX_LISTCTRL, B_TX_LISTDONE); in hdmitx_hdcp_ResumeRepeaterAuthenticate()
2771 it6161_hdmi_tx_write(it6161, REG_TX_LISTCTRL, 0x00); in hdmitx_hdcp_ResumeRepeaterAuthenticate()
2772 it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERHDCP); in hdmitx_hdcp_ResumeRepeaterAuthenticate()
2969 static SYS_STATUS hdmi_tx_hdcp_get_ksv_list(struct it6161 *it6161, u8 *pKSVList,u8 cDownStream) in hdmi_tx_hdcp_get_ksv_list() argument
2981 it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL, B_TX_MASTERHOST); in hdmi_tx_hdcp_get_ksv_list()
2982 it6161_hdmi_tx_write(it6161, REG_TX_DDC_HEADER, 0x74); in hdmi_tx_hdcp_get_ksv_list()
2983 it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQOFF, 0x43); in hdmi_tx_hdcp_get_ksv_list()
2984 it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQCOUNT, cDownStream * 5); in hdmi_tx_hdcp_get_ksv_list()
2985 it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD, CMD_DDC_SEQ_BURSTREAD); in hdmi_tx_hdcp_get_ksv_list()
2987 ucdata = it6161_ddc_wait(it6161); in hdmi_tx_hdcp_get_ksv_list()
2996 pKSVList[timeout] = it6161_hdmi_tx_read(it6161, REG_TX_DDC_READFIFO); in hdmi_tx_hdcp_get_ksv_list()
3007 static SYS_STATUS hdmitx_hdcp_GetVr(struct it6161 *it6161, u8 *pVr) in hdmitx_hdcp_GetVr() argument
3015 it6161_hdmi_tx_write(it6161, REG_TX_DDC_MASTER_CTRL,B_TX_MASTERHOST); in hdmitx_hdcp_GetVr()
3016 it6161_hdmi_tx_write(it6161, REG_TX_DDC_HEADER,0x74); in hdmitx_hdcp_GetVr()
3017 it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQOFF,0x20); in hdmitx_hdcp_GetVr()
3018 it6161_hdmi_tx_write(it6161, REG_TX_DDC_REQCOUNT,20); in hdmitx_hdcp_GetVr()
3019 it6161_hdmi_tx_write(it6161, REG_TX_DDC_CMD,CMD_DDC_SEQ_BURSTREAD); in hdmitx_hdcp_GetVr()
3021 ucdata = it6161_ddc_wait(it6161); in hdmitx_hdcp_GetVr()
3027 it6161_hdmi_tx_change_bank(it6161, 0); in hdmitx_hdcp_GetVr()
3031 it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL ,timeout); in hdmitx_hdcp_GetVr()
3032 pVr[timeout*4] = (u32)it6161_hdmi_tx_read(it6161, REG_TX_SHA_RD_BYTE1); in hdmitx_hdcp_GetVr()
3033 pVr[timeout*4+1] = (u32)it6161_hdmi_tx_read(it6161, REG_TX_SHA_RD_BYTE2); in hdmitx_hdcp_GetVr()
3034 pVr[timeout*4+2] = (u32)it6161_hdmi_tx_read(it6161, REG_TX_SHA_RD_BYTE3); in hdmitx_hdcp_GetVr()
3035 pVr[timeout*4+3] = (u32)it6161_hdmi_tx_read(it6161, REG_TX_SHA_RD_BYTE4); in hdmitx_hdcp_GetVr()
3041 static SYS_STATUS hdmitx_hdcp_GetM0(struct it6161 *it6161, u8 *pM0) in hdmitx_hdcp_GetM0() argument
3049 it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL,5); // read m0[31:0] from reg51~reg54 in hdmitx_hdcp_GetM0()
3050 pM0[0] = it6161_hdmi_tx_read(it6161, REG_TX_SHA_RD_BYTE1); in hdmitx_hdcp_GetM0()
3051 pM0[1] = it6161_hdmi_tx_read(it6161, REG_TX_SHA_RD_BYTE2); in hdmitx_hdcp_GetM0()
3052 pM0[2] = it6161_hdmi_tx_read(it6161, REG_TX_SHA_RD_BYTE3); in hdmitx_hdcp_GetM0()
3053 pM0[3] = it6161_hdmi_tx_read(it6161, REG_TX_SHA_RD_BYTE4); in hdmitx_hdcp_GetM0()
3054 it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL,0); // read m0[39:32] from reg55 in hdmitx_hdcp_GetM0()
3055 pM0[4] = it6161_hdmi_tx_read(it6161, REG_TX_AKSV_RD_BYTE5); in hdmitx_hdcp_GetM0()
3056 it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL,1); // read m0[47:40] from reg55 in hdmitx_hdcp_GetM0()
3057 pM0[5] = it6161_hdmi_tx_read(it6161, REG_TX_AKSV_RD_BYTE5); in hdmitx_hdcp_GetM0()
3058 it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL,2); // read m0[55:48] from reg55 in hdmitx_hdcp_GetM0()
3059 pM0[6] = it6161_hdmi_tx_read(it6161, REG_TX_AKSV_RD_BYTE5); in hdmitx_hdcp_GetM0()
3060 it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL,3); // read m0[63:56] from reg55 in hdmitx_hdcp_GetM0()
3061 pM0[7] = it6161_hdmi_tx_read(it6161, REG_TX_AKSV_RD_BYTE5); in hdmitx_hdcp_GetM0()
3088 hdmi_tx_hdcp_reset_auth(it6161); in TxHDCP_chg()
3093 hdmi_tx_hdcp_reset_auth(it6161); in TxHDCP_chg()
3098 hdmi_tx_hdcp_reset_auth(it6161); in TxHDCP_chg()
3121 hdmi_tx_hdcp_reset_auth(it6161); in TxHDCP_chg()
3126 hdmitx_hdcp_CancelRepeaterAuthenticate(it6161); in TxHDCP_chg()
3127 hdmi_tx_hdcp_reset_auth(it6161); in TxHDCP_chg()
3132 hdmitx_hdcp_ResumeRepeaterAuthenticate(it6161); in TxHDCP_chg()
3134 it6161_hdmi_tx_set_av_mute(it6161, false) ; in TxHDCP_chg()
3170 it6161_hdmi_tx_change_bank(it6161, 0); in TxHDCP_fsm()
3174 … ucdata = it6161_hdmi_tx_read(it6161, REG_TX_SYS_STATUS)& (B_TX_HPDETECT|B_TX_RXSENDETECT); in TxHDCP_fsm()
3183 if(hdmi_tx_get_hdcp_bcaps_bstatus(it6161, &BCaps,&BStatus) != ER_SUCCESS) in TxHDCP_fsm()
3190 if(B_TX_HDMI_MODE == (it6161_hdmi_tx_read(it6161, REG_TX_HDMI_MODE) & B_TX_HDMI_MODE )) in TxHDCP_fsm()
3212 hdmi_tx_hdcp_get_bksv(it6161, bksv, ARRAY_SIZE(bksv)); in TxHDCP_fsm()
3227 …it6161_hdmi_tx_change_bank(it6161, 0); // switch bank action should start on direct register writt… in TxHDCP_fsm()
3229 it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_TX_HDCP_RST_HDMITX, 0x00); in TxHDCP_fsm()
3231 it6161_hdmi_tx_write(it6161, REG_TX_HDCP_DESIRE,8|B_TX_CPDESIRE); in TxHDCP_fsm()
3232 hdmi_tx_hdcp_clear_auth_interrupt(it6161); in TxHDCP_fsm()
3234 hdmi_tx_hdcp_generate_an(it6161); in TxHDCP_fsm()
3235 it6161_hdmi_tx_write(it6161, REG_TX_LISTCTRL,0); in TxHDCP_fsm()
3238 it6161_hdmi_tx_clear_ddc_fifo(it6161); in TxHDCP_fsm()
3239 hdmi_tx_hdcp_auth_fire(it6161); in TxHDCP_fsm()
3271 ucdata = it6161_hdmi_tx_read(it6161, REG_TX_AUTH_STAT); in TxHDCP_fsm()
3309 if(hdmi_tx_get_hdcp_bcaps_bstatus(it6161, &BCaps,&BStatus) == ER_FAIL) in TxHDCP_fsm()
3321 it6161_hdmi_tx_clear_ddc_fifo(it6161); in TxHDCP_fsm()
3322 it6161_hdmi_tx_generate_ddc_sclk(it6161); in TxHDCP_fsm()
3354 if(hdmi_tx_hdcp_get_ksv_list(it6161, KSVList,cDownStream) == ER_FAIL) in TxHDCP_fsm()
3361 if(hdmitx_hdcp_GetVr(it6161, Vr) == ER_FAIL) in TxHDCP_fsm()
3367 if(hdmitx_hdcp_GetM0(it6161, M0) == ER_FAIL) in TxHDCP_fsm()
3429 static SYS_STATUS hdmi_tx_hdcp_auth_process_Repeater(struct it6161 *it6161) in hdmi_tx_hdcp_auth_process_Repeater() argument
3461 hdmi_tx_get_hdcp_bcaps_bstatus(it6161, &BCaps,&BStatus); in hdmi_tx_hdcp_auth_process_Repeater()
3463 if((B_TX_INT_HPD_PLUG|B_TX_INT_RX_SENSE)&it6161_hdmi_tx_read(it6161, REG_TX_INT_STAT1)) in hdmi_tx_hdcp_auth_process_Repeater()
3468 hdmi_tx_hdcp_auth_fire(it6161); in hdmi_tx_hdcp_auth_process_Repeater()
3472 if((B_TX_INT_HPD_PLUG|B_TX_INT_RX_SENSE)&it6161_hdmi_tx_read(it6161, REG_TX_INT_STAT1)) in hdmi_tx_hdcp_auth_process_Repeater()
3481 if((B_TX_INT_HPD_PLUG|B_TX_INT_RX_SENSE)&it6161_hdmi_tx_read(it6161, REG_TX_INT_STAT1)) in hdmi_tx_hdcp_auth_process_Repeater()
3486 uc = it6161_hdmi_tx_read(it6161, REG_TX_INT_STAT1); in hdmi_tx_hdcp_auth_process_Repeater()
3492 uc = it6161_hdmi_tx_read(it6161, REG_TX_INT_STAT2); in hdmi_tx_hdcp_auth_process_Repeater()
3509 it6161_hdmi_tx_write(it6161, REG_TX_INT_CLR0,B_TX_CLR_KSVLISTCHK); in hdmi_tx_hdcp_auth_process_Repeater()
3510 it6161_hdmi_tx_write(it6161, REG_TX_INT_CLR1,0); in hdmi_tx_hdcp_auth_process_Repeater()
3511 it6161_hdmi_tx_write(it6161, REG_TX_SYS_STATUS,B_TX_INTACTDONE); in hdmi_tx_hdcp_auth_process_Repeater()
3512 it6161_hdmi_tx_write(it6161, REG_TX_SYS_STATUS,0); in hdmi_tx_hdcp_auth_process_Repeater()
3530 if((B_TX_INT_HPD_PLUG|B_TX_INT_RX_SENSE)&it6161_hdmi_tx_read(it6161, REG_TX_INT_STAT1)) in hdmi_tx_hdcp_auth_process_Repeater()
3535 if(hdmi_tx_get_hdcp_bcaps_bstatus(it6161, &BCaps,&BStatus) == ER_FAIL) in hdmi_tx_hdcp_auth_process_Repeater()
3555 it6161_hdmi_tx_clear_ddc_fifo(it6161); in hdmi_tx_hdcp_auth_process_Repeater()
3556 it6161_hdmi_tx_generate_ddc_sclk(it6161); in hdmi_tx_hdcp_auth_process_Repeater()
3565 if(hdmi_tx_hdcp_get_ksv_list(it6161, KSVList,cDownStream) == ER_FAIL) in hdmi_tx_hdcp_auth_process_Repeater()
3588 if(hdmitx_hdcp_GetVr(it6161, Vr) == ER_FAIL) in hdmi_tx_hdcp_auth_process_Repeater()
3592 if(hdmitx_hdcp_GetM0(it6161, M0) == ER_FAIL) in hdmi_tx_hdcp_auth_process_Repeater()
3601 if((B_TX_INT_HPD_PLUG|B_TX_INT_RX_SENSE)&it6161_hdmi_tx_read(it6161, REG_TX_INT_STAT1)) in hdmi_tx_hdcp_auth_process_Repeater()
3608 hdmitx_hdcp_ResumeRepeaterAuthenticate(it6161); in hdmi_tx_hdcp_auth_process_Repeater()
3613 hdmitx_hdcp_CancelRepeaterAuthenticate(it6161); in hdmi_tx_hdcp_auth_process_Repeater()
3618 static int hdmi_tx_hdcp_get_m0(struct it6161 *it6161, u8 *m0)
3626 it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL, 5);
3627 ret = it6161_hdmi_tx_burst_read(it6161, REG_TX_SHA_RD_BYTE1, m0, 4);
3636 it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL, i);
3637 m0[4 + i] = it6161_hdmi_tx_read(it6161, REG_TX_AKSV_RD_BYTE5);
3644 static int hdmi_tx_hdcp_get_bcaps(struct it6161 *it6161) in hdmi_tx_hdcp_get_bcaps() argument
3648 …hdmi_tx_ddc_operation(it6161, DDC_HDCP_ADDRESS, DRM_HDCP_DDC_BCAPS, 0x01, 0x00, CMD_DDC_SEQ_BURSTR… in hdmi_tx_hdcp_get_bcaps()
3649 ret = it6161_ddc_wait(it6161); in hdmi_tx_hdcp_get_bcaps()
3656 ret = it6161_hdmi_tx_read(it6161, REG_TX_BCAP); in hdmi_tx_hdcp_get_bcaps()
3666 static int hdmi_tx_hdcp_get_bstatus(struct it6161 *it6161) in hdmi_tx_hdcp_get_bstatus() argument
3670 …hdmi_tx_ddc_operation(it6161, DDC_HDCP_ADDRESS, DRM_HDCP_DDC_BSTATUS, 0x02, 0x00, CMD_DDC_SEQ_BURS… in hdmi_tx_hdcp_get_bstatus()
3671 ret = it6161_ddc_wait(it6161); in hdmi_tx_hdcp_get_bstatus()
3678 ret = it6161_hdmi_tx_read(it6161, REG_TX_BSTAT); in hdmi_tx_hdcp_get_bstatus()
3687 ret = it6161_hdmi_tx_read(it6161, REG_TX_BSTAT + 1); in hdmi_tx_hdcp_get_bstatus()
3700 static void hdmi_tx_hdcp_show_ksv_list(struct it6161 *it6161, u8 *ksvlist)
3704 for (i = 0; i < it6161->hdcp_downstream_count; i++, ksvlist += DRM_HDCP_KSV_LEN)
3708 static int hdmi_tx_hdcp_get_ksv_list1(struct it6161 *it6161, u8 *ksvlist, size_t size)
3712 …hdmi_tx_ddc_operation(it6161, DDC_HDCP_ADDRESS, DRM_HDCP_DDC_KSV_FIFO, size, 0x00, CMD_DDC_SEQ_BUR…
3713 ret = it6161_ddc_wait(it6161);
3721 ret = it6161_hdmi_tx_read(it6161, REG_TX_DDC_READFIFO);
3734 static int hdmi_tx_hdcp_get_v_prime(struct it6161 *it6161, u8 *v_prime, size_t size)
3738 …hdmi_tx_ddc_operation(it6161, DDC_HDCP_ADDRESS, DRM_HDCP_DDC_V_PRIME(0), size, 0x00, CMD_DDC_SEQ_B…
3739 ret = it6161_ddc_wait(it6161);
3747 it6161_hdmi_tx_write(it6161, REG_TX_SHA_SEL ,i);
3748 ret = it6161_hdmi_tx_burst_read(it6161, REG_TX_SHA_RD_BYTE1, v_prime, DRM_HDCP_V_PRIME_PART_LEN);
3760 static int hdmi_tx_setup_sha1_input(struct it6161 *it6161, u8 *ksvlist, u8 *sha1_input)
3764 hdmi_tx_hdcp_get_m0(it6161, m0);
3766 for (i = 0; i < it6161->hdcp_downstream_count * DRM_HDCP_KSV_LEN; i++)
3770 sha1_input[msg_count++] = (u8)it6161->bstatus;
3771 sha1_input[msg_count++] = (u8)(it6161->bstatus >> 8);
3780 static int it6161_sha1_digest(struct it6161 *it6161, u8 *sha1_input,
3786 struct device *dev = &it6161->i2c_mipi_rx->dev;
3809 static bool hdmi_tX_hdcp_compare_sha1_v_prime_v(struct it6161 *it6161, u8 *v_array, u8 *v_prime_arr…
3829 struct it6161 *it6161 = container_of(work, struct it6161,
3837 if (!hdmi_tx_get_sink_hpd(it6161))
3840 ret = hdmi_tx_hdcp_get_bcaps(it6161);
3858 ret = hdmi_tx_hdcp_get_ksv_list1(it6161, ksvlist, ARRAY_SIZE(ksvlist));
3863 hdmi_tx_hdcp_show_ksv_list(it6161, ksvlist);
3864 ret = hdmi_tx_setup_sha1_input(it6161, ksvlist, it6161->sha1_transform_input);
3865 DRM_INFO("sha1 msg_count :%d \nsha1_input:0x %*ph", ret, ret, it6161->sha1_transform_input);
3866 ret = it6161_sha1_digest(it6161, it6161->sha1_transform_input, ret, (u8 *)v);
3874 ret = hdmi_tx_hdcp_get_v_prime(it6161, (u8 *)v_prime, sizeof(v_prime));
3883 ret = hdmi_tX_hdcp_compare_sha1_v_prime_v(it6161, (u8 *)v, (u8 *)v_prime);
3887 it6161_hdmi_tx_set_bits(it6161, REG_TX_LISTCTRL, B_TX_LISTDONE , B_TX_LISTDONE);
3889 …it6161_hdmi_tx_set_bits(it6161, REG_TX_LISTCTRL, B_TX_LISTDONE | B_TX_LISTFAIL, B_TX_LISTDONE | B_…
3891 it6161_hdmi_tx_set_bits(it6161, REG_TX_LISTCTRL, B_TX_LISTDONE | B_TX_LISTFAIL, 0x00);
3895 static bool hdmi_tx_hdcp_enable_auth_part1(struct it6161 *it6161) in hdmi_tx_hdcp_enable_auth_part1() argument
3900 ret = hdmi_tx_hdcp_get_bksv(it6161, it6161->bksv, (int)ARRAY_SIZE(it6161->bksv)); in hdmi_tx_hdcp_enable_auth_part1()
3903 DRM_INFO("bksv: 0x %*ph", (int)ARRAY_SIZE(it6161->bksv), it6161->bksv); in hdmi_tx_hdcp_enable_auth_part1()
3905 for (i = 0; i < ARRAY_SIZE(it6161->bksv); i++) in hdmi_tx_hdcp_enable_auth_part1()
3906 count += countbit(it6161->bksv[i]); in hdmi_tx_hdcp_enable_auth_part1()
3913 if ((it6161->bksv[4] == 0x93) && in hdmi_tx_hdcp_enable_auth_part1()
3914 (it6161->bksv[3] == 0x43) && in hdmi_tx_hdcp_enable_auth_part1()
3915 (it6161->bksv[2] == 0x5C) && in hdmi_tx_hdcp_enable_auth_part1()
3916 (it6161->bksv[1] == 0xDE) && in hdmi_tx_hdcp_enable_auth_part1()
3917 (it6161->bksv[0] == 0x23)) { in hdmi_tx_hdcp_enable_auth_part1()
3922 it6161_hdmi_tx_write(it6161, REG_TX_HDCP_DESIRE, 0x08 | B_TX_CPDESIRE); in hdmi_tx_hdcp_enable_auth_part1()
3923 hdmi_tx_hdcp_generate_an(it6161); in hdmi_tx_hdcp_enable_auth_part1()
3924 hdmi_tx_hdcp_auth_fire(it6161); in hdmi_tx_hdcp_enable_auth_part1()
3929 static bool hdmi_tx_hdcp_auth_process(struct it6161 *it6161) in hdmi_tx_hdcp_auth_process() argument
3939 it6161->hdmi_tx_hdcp_retry--; in hdmi_tx_hdcp_auth_process()
3940 hdmi_tx_hdcp_reset_auth(it6161); in hdmi_tx_hdcp_auth_process()
3941 it6161_hdmi_tx_change_bank(it6161, 0); in hdmi_tx_hdcp_auth_process()
3942 it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_TX_HDCP_RST_HDMITX, 0x00); in hdmi_tx_hdcp_auth_process()
3943 it6161_hdmi_tx_write(it6161, REG_TX_LISTCTRL, 0x00); in hdmi_tx_hdcp_auth_process()
3944 it6161_hdmi_tx_clear_ddc_fifo(it6161); in hdmi_tx_hdcp_auth_process()
3945 hdmi_tx_hdcp_int_mask_enable(it6161); in hdmi_tx_hdcp_auth_process()
3948 ret = hdmi_tx_hdcp_get_bstatus(it6161); in hdmi_tx_hdcp_auth_process()
3951 it6161->bstatus = (u16)ret; in hdmi_tx_hdcp_auth_process()
3953 ret = hdmi_tx_hdcp_get_bcaps(it6161); in hdmi_tx_hdcp_auth_process()
3963 DRM_INFO("bcaps: 0x%02x, bstatus: 0x%04x, hdmi_mode: %d", bcaps, it6161->bstatus, in hdmi_tx_hdcp_auth_process()
3964 it6161->bstatus & B_TX_CAP_HDMI_MODE); in hdmi_tx_hdcp_auth_process()
3965 it6161->is_repeater = !!(bcaps & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT); in hdmi_tx_hdcp_auth_process()
3966 DRM_INFO("downstream is hdcp %s", it6161->is_repeater ? "repeater" : "receiver"); in hdmi_tx_hdcp_auth_process()
3967 if (it6161->is_repeater) { in hdmi_tx_hdcp_auth_process()
3968 it6161->hdcp_downstream_count = (u8)DRM_HDCP_NUM_DOWNSTREAM(it6161->bstatus); in hdmi_tx_hdcp_auth_process()
3969 DRM_INFO("down stream Count %d", it6161->hdcp_downstream_count); in hdmi_tx_hdcp_auth_process()
3970 if (it6161->hdcp_downstream_count > 6) { in hdmi_tx_hdcp_auth_process()
3976 ret = hdmi_tx_hdcp_enable_auth_part1(it6161); in hdmi_tx_hdcp_auth_process()
3981 if (!it6161->is_repeater) { in hdmi_tx_hdcp_auth_process()
3982 ret = wait_for_completion_timeout(&it6161->wait_hdcp_event, msecs_to_jiffies(1000)); in hdmi_tx_hdcp_auth_process()
3993 static void hdmitx_hdcp_ResumeAuthentication(struct it6161 *it6161) in hdmitx_hdcp_ResumeAuthentication() argument
3995 it6161_hdmi_tx_set_av_mute(it6161, true); in hdmitx_hdcp_ResumeAuthentication()
3996 if(hdmi_tx_hdcp_auth_process(it6161) == ER_SUCCESS) in hdmitx_hdcp_ResumeAuthentication()
3999 it6161_hdmi_tx_set_av_mute(it6161, false); in hdmitx_hdcp_ResumeAuthentication()
4004 struct it6161 *it6161 = container_of(work, struct it6161, in hdmi_tx_hdcp_work() local
4007 bool ret, sink_hpd = hdmi_tx_get_sink_hpd(it6161), video_state = hdmi_tx_get_video_state(it6161); in hdmi_tx_hdcp_work()
4009 if (it6161->hdmi_tx_hdcp_retry <= 0 || !sink_hpd || !video_state) { in hdmi_tx_hdcp_work()
4010 …DRM_INFO("hdcp_retry:%d sink_hpd:%d video_stable_state:%d", it6161->hdmi_tx_hdcp_retry, sink_hpd, … in hdmi_tx_hdcp_work()
4014 ret = hdmi_tx_hdcp_auth_process(it6161); in hdmi_tx_hdcp_work()
4015 if (it6161->is_repeater) { in hdmi_tx_hdcp_work()
4023 static void hdmi_tx_enable_hdcp(struct it6161 *it6161) in hdmi_tx_enable_hdcp() argument
4025 struct device *dev = &it6161->i2c_hdmi_tx->dev; in hdmi_tx_enable_hdcp()
4028 queue_delayed_work(system_wq, &it6161->hdcp_work, in hdmi_tx_enable_hdcp()
4035 …x reg0x61:0x%02x", __func__, it6161_hdmi_tx_read(it6161, REG_TX_SYS_STATUS), it6161_hdmi_tx_read(i… in getHDMITX_LinkStatus()
4036 if(B_TX_RXSENDETECT & it6161_hdmi_tx_read(it6161, REG_TX_SYS_STATUS)) { in getHDMITX_LinkStatus()
4037 if(0==it6161_hdmi_tx_read(it6161, REG_TX_AFE_DRV_CTRL)) in getHDMITX_LinkStatus()
4053 static void hdmi_tx_setup_pclk_div2(struct it6161 *it6161) in hdmi_tx_setup_pclk_div2() argument
4057 it6161_hdmi_tx_set_bits(it6161, REG_TX_INPUT_MODE, B_TX_PCLKDIV2, B_TX_PCLKDIV2); in hdmi_tx_setup_pclk_div2()
4080 static void hdmi_tx_setup_csc(struct it6161 *it6161) in hdmi_tx_setup_csc() argument
4083 u8 input_mode = it6161->hdmi_tx_input_color_space; in hdmi_tx_setup_csc()
4084 u8 output_mode = it6161->hdmi_tx_output_color_space; in hdmi_tx_setup_csc()
4210 …for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ it6161_hdmi_tx_write(it6161, REG_TX_CSC_YOFF+i,bCSCMtx_RGB… in hdmi_tx_setup_csc()
4214 …for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ it6161_hdmi_tx_write(it6161, REG_TX_CSC_YOFF+i,bCSCMtx_RGB… in hdmi_tx_setup_csc()
4218 …for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ it6161_hdmi_tx_write(it6161, REG_TX_CSC_YOFF+i,bCSCMtx_RGB… in hdmi_tx_setup_csc()
4223 …for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ it6161_hdmi_tx_write(it6161, REG_TX_CSC_YOFF+i,bCSCMtx_RGB… in hdmi_tx_setup_csc()
4238 …for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ it6161_hdmi_tx_write(it6161, REG_TX_CSC_YOFF+i,bCSCMtx_YUV… in hdmi_tx_setup_csc()
4242 …for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ it6161_hdmi_tx_write(it6161, REG_TX_CSC_YOFF+i,bCSCMtx_YUV… in hdmi_tx_setup_csc()
4246 …for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ it6161_hdmi_tx_write(it6161, REG_TX_CSC_YOFF+i,bCSCMtx_YUV… in hdmi_tx_setup_csc()
4251 …for( i = 0 ; i < SIZEOF_CSCMTX ; i++ ){ it6161_hdmi_tx_write(it6161, REG_TX_CSC_YOFF+i,bCSCMtx_YUV… in hdmi_tx_setup_csc()
4262 it6161_hdmi_tx_set_bits(it6161, 0xF, 0x10, 0x10); in hdmi_tx_setup_csc()
4266 it6161_hdmi_tx_set_bits(it6161, 0xF, 0x10, 0x00); in hdmi_tx_setup_csc()
4268 …ucData = it6161_hdmi_tx_read(it6161, REG_TX_CSC_CTRL) & ~(M_TX_CSC_SEL|B_TX_DNFREE_GO|B_TX_EN_DITH… in hdmi_tx_setup_csc()
4271 it6161_hdmi_tx_write(it6161, REG_TX_CSC_CTRL,ucData); in hdmi_tx_setup_csc()
4281 static void hdmi_tx_setup_afe(struct it6161 *it6161, VIDEOPCLKLEVEL level) in hdmi_tx_setup_afe() argument
4284 it6161_hdmi_tx_write(it6161, REG_TX_AFE_DRV_CTRL, B_TX_AFE_DRV_RST); in hdmi_tx_setup_afe()
4288 it6161_hdmi_tx_set_bits(it6161, 0x62, 0x90, 0x80); in hdmi_tx_setup_afe()
4289 it6161_hdmi_tx_set_bits(it6161, 0x64, 0x89, 0x80); in hdmi_tx_setup_afe()
4290 it6161_hdmi_tx_set_bits(it6161, 0x68, 0x10, 0x00); in hdmi_tx_setup_afe()
4291 … it6161_hdmi_tx_set_bits(it6161, 0x66, 0x80, 0x80);//hdmitxset(0x66, 0x80, 0x80);// mark fix 6017 in hdmi_tx_setup_afe()
4294 it6161_hdmi_tx_set_bits(it6161, 0x62, 0x90, 0x10); in hdmi_tx_setup_afe()
4295 it6161_hdmi_tx_set_bits(it6161, 0x64, 0x89, 0x09); in hdmi_tx_setup_afe()
4296 it6161_hdmi_tx_set_bits(it6161, 0x68, 0x10, 0x10); in hdmi_tx_setup_afe()
4313 it6161_hdmi_tx_set_bits(it6161, 0x6A, 0xFF, 0x5D); in hdmi_tx_setup_afe()
4320 static void hdmi_tx_fire_afe(struct it6161 *it6161) in hdmi_tx_fire_afe() argument
4322 it6161_hdmi_tx_change_bank(it6161, 0x00); in hdmi_tx_fire_afe()
4323 it6161_hdmi_tx_write(it6161, REG_TX_AFE_DRV_CTRL, 0x00); in hdmi_tx_fire_afe()
4348 static void hdmi_tx_disable_video_output(struct it6161 *it6161) in hdmi_tx_disable_video_output() argument
4350 it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_HDMITX_VID_RST, B_HDMITX_VID_RST); in hdmi_tx_disable_video_output()
4351 it6161_hdmi_tx_write(it6161, REG_TX_AFE_DRV_CTRL,B_TX_AFE_DRV_RST|B_TX_AFE_DRV_PWD); in hdmi_tx_disable_video_output()
4352 it6161_hdmi_tx_set_bits(it6161, 0x62, 0x90, 0x00); in hdmi_tx_disable_video_output()
4353 it6161_hdmi_tx_set_bits(it6161, 0x64, 0x89, 0x00); in hdmi_tx_disable_video_output()
4356 static void hdmi_tx_enable_video_output(struct it6161 *it6161, VIDEOPCLKLEVEL level) in hdmi_tx_enable_video_output() argument
4358 …it6161_hdmi_tx_write(it6161, REG_TX_SW_RST, B_HDMITX_AUD_RST | B_TX_AREF_RST | B_TX_HDCP_RST_HDMIT… in hdmi_tx_enable_video_output()
4359 it6161_hdmi_tx_change_bank(it6161, 1); in hdmi_tx_enable_video_output()
4360 it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB1, 0x00); in hdmi_tx_enable_video_output()
4361 it6161_hdmi_tx_change_bank(it6161, 0); in hdmi_tx_enable_video_output()
4363 if(it6161->hdmi_mode) in hdmi_tx_enable_video_output()
4364 it6161_hdmi_tx_set_av_mute(it6161, true); in hdmi_tx_enable_video_output()
4366 hdmi_tx_setup_pclk_div2(it6161); in hdmi_tx_enable_video_output()
4367 hdmi_tx_setup_csc(it6161); in hdmi_tx_enable_video_output()
4368 it6161_hdmi_tx_write(it6161, REG_TX_HDMI_MODE, it6161->hdmi_mode ? B_TX_HDMI_MODE : B_TX_DVI_MODE); in hdmi_tx_enable_video_output()
4369 hdmi_tx_setup_afe(it6161, level); in hdmi_tx_enable_video_output()
4370 hdmi_tx_fire_afe(it6161); in hdmi_tx_enable_video_output()
4377 static void setHDMITX_ChStat(struct it6161 *it6161, u8 ucIEC60958ChStat[]) in setHDMITX_ChStat() argument
4381 it6161_hdmi_tx_change_bank(it6161, 1); in setHDMITX_ChStat()
4383 it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_MODE,uc); in setHDMITX_ChStat()
4384 it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_CAT,ucIEC60958ChStat[1]); // 192, audio CATEGORY in setHDMITX_ChStat()
4385 it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_SRCNUM,ucIEC60958ChStat[2]&0xF); in setHDMITX_ChStat()
4386 it6161_hdmi_tx_write(it6161, REG_TX_AUD0CHST_CHTNUM,(ucIEC60958ChStat[2]>>4)&0xF); in setHDMITX_ChStat()
4387 it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_CA_FS,ucIEC60958ChStat[3]); // choose clock in setHDMITX_ChStat()
4388 it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_OFS_WL,ucIEC60958ChStat[4]); in setHDMITX_ChStat()
4389 it6161_hdmi_tx_change_bank(it6161, 0); in setHDMITX_ChStat()
4485 it6161_hdmi_tx_change_bank(it6161, 0); in setHDMITX_LPCMAudio()
4486 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0,AudioEnable&0xF0); in setHDMITX_LPCMAudio()
4488 …it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL1,AudioFormat); // regE1 bOutputAudioMode should be … in setHDMITX_LPCMAudio()
4490 it6161_hdmi_tx_set_bits(it6161, 0x5A,0x02, 0x00); in setHDMITX_LPCMAudio()
4493 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping. in setHDMITX_LPCMAudio()
4497 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xFF); // default mapping. in setHDMITX_LPCMAudio()
4500 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping. in setHDMITX_LPCMAudio()
4506 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3,B_TX_CHSTSEL); in setHDMITX_LPCMAudio()
4510 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3,0); in setHDMITX_LPCMAudio()
4513 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3,0); in setHDMITX_LPCMAudio()
4516 it6161_hdmi_tx_write(it6161, REG_TX_AUD_SRCVALID_FLAT,0x00); in setHDMITX_LPCMAudio()
4517 it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO,0x00); // regE5 = 0 ; in setHDMITX_LPCMAudio()
4522 it6161_hdmi_tx_set_bits(it6161, 0x5c,(1<<6), (1<<6)); in setHDMITX_LPCMAudio()
4525 if(it6161_hdmi_tx_read(it6161, REG_TX_CLK_STATUS2) & B_TX_OSF_LOCK) in setHDMITX_LPCMAudio()
4533 bTDMSetting = it6161_hdmi_tx_read(it6161, REG_TX_AUD_HDAUDIO) ; in setHDMITX_LPCMAudio()
4544 … it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO, bTDMSetting) ; // 2 channel NLPCM, no TDM mode. in setHDMITX_LPCMAudio()
4563 it6161_hdmi_tx_change_bank(it6161, 0); in setHDMITX_NLPCMAudio()
4565 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, AudioEnable); in setHDMITX_NLPCMAudio()
4568 …it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL1,0x01); // regE1 bOutputAudioMode should be loaded … in setHDMITX_NLPCMAudio()
4572 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping. in setHDMITX_NLPCMAudio()
4576 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xFF); // default mapping. in setHDMITX_NLPCMAudio()
4579 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping. in setHDMITX_NLPCMAudio()
4583 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3,B_TX_CHSTSEL); in setHDMITX_NLPCMAudio()
4585 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3,0); in setHDMITX_NLPCMAudio()
4588 it6161_hdmi_tx_write(it6161, REG_TX_AUD_SRCVALID_FLAT,0x00); in setHDMITX_NLPCMAudio()
4589 it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO,0x00); // regE5 = 0 ; in setHDMITX_NLPCMAudio()
4595 if(it6161_hdmi_tx_read(it6161, REG_TX_CLK_STATUS2) & B_TX_OSF_LOCK) in setHDMITX_NLPCMAudio()
4603 i = it6161_hdmi_tx_read(it6161, REG_TX_AUD_HDAUDIO) ; in setHDMITX_NLPCMAudio()
4605 it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO, i) ; // 2 channel NLPCM, no TDM mode. in setHDMITX_NLPCMAudio()
4607 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, AudioEnable|B_TX_AUD_EN_I2S0); in setHDMITX_NLPCMAudio()
4613 it6161_hdmi_tx_change_bank(it6161, 0); in setHDMITX_HBRAudio()
4620 …it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL1,0x47); // regE1 bOutputAudioMode should be loaded … in setHDMITX_HBRAudio()
4624 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping. in setHDMITX_HBRAudio()
4628 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xFF); // default mapping. in setHDMITX_HBRAudio()
4631 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping. in setHDMITX_HBRAudio()
4636 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT|B_TX_AUD_SPDIF); in setHDMITX_HBRAudio()
4637 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3,B_TX_CHSTSEL); in setHDMITX_HBRAudio()
4641 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT); in setHDMITX_HBRAudio()
4642 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3,0); in setHDMITX_HBRAudio()
4644 it6161_hdmi_tx_write(it6161, REG_TX_AUD_SRCVALID_FLAT,0x08); in setHDMITX_HBRAudio()
4645 it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO,B_TX_HBR); // regE5 = 0 ; in setHDMITX_HBRAudio()
4656 if(it6161_hdmi_tx_read(it6161, REG_TX_CLK_STATUS2) & B_TX_OSF_LOCK) in setHDMITX_HBRAudio()
4661 … it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT|B_TX_AUD_SPDIF|B_TX_AUD_EN_SPDIF); in setHDMITX_HBRAudio()
4665 …it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT|B_TX_AUD_EN_I2S3|B_TX_AUD_EN_I2S2|… in setHDMITX_HBRAudio()
4667 it6161_hdmi_tx_set_bits(it6161, 0x5c, BIT(6), 0x00); in setHDMITX_HBRAudio()
4668 hdmiTxDev[0].bAudioChannelEnable=it6161_hdmi_tx_read(it6161, REG_TX_AUDIO_CTRL0); in setHDMITX_HBRAudio()
4680 …it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL1,0x41); // regE1 bOutputAudioMode should be loaded … in setHDMITX_DSDAudio()
4681 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_FIFOMAP,0xE4); // default mapping. in setHDMITX_DSDAudio()
4683 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT); in setHDMITX_DSDAudio()
4684 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL3,0); in setHDMITX_DSDAudio()
4686 it6161_hdmi_tx_write(it6161, REG_TX_AUD_SRCVALID_FLAT,0x00); in setHDMITX_DSDAudio()
4687 it6161_hdmi_tx_write(it6161, REG_TX_AUD_HDAUDIO,B_TX_DSD); // regE5 = 0 ; in setHDMITX_DSDAudio()
4694 …it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, M_TX_AUD_24BIT|B_TX_AUD_EN_I2S3|B_TX_AUD_EN_I2S2|… in setHDMITX_DSDAudio()
4697 static void HDMITX_DisableAudioOutput(struct it6161 *it6161) in HDMITX_DisableAudioOutput() argument
4703 …it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, (B_HDMITX_AUD_RST | B_TX_AREF_RST), (B_HDMITX_AUD_R… in HDMITX_DisableAudioOutput()
4704 it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x10, 0x10 ); in HDMITX_DisableAudioOutput()
4707 static void HDMITX_EnableAudioOutput(struct it6161 *it6161, u8 AudioType, u8 bAudInterface /*I2S/SP… in HDMITX_EnableAudioOutput() argument
4722 …it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST,(B_HDMITX_AUD_RST | B_TX_AREF_RST), (B_HDMITX_AUD_RS… in HDMITX_EnableAudioOutput()
4723 … it6161_hdmi_tx_write(it6161, REG_TX_CLK_CTRL0,B_TX_AUTO_OVER_SAMPLING_CLOCK|B_TX_EXT_256FS|0x01); in HDMITX_EnableAudioOutput()
4725 it6161_hdmi_tx_set_bits(it6161, 0x0F, 0x10, 0x00 ); // power on the ACLK in HDMITX_EnableAudioOutput()
4731 it6161_hdmi_tx_write(it6161, REG_TX_CLK_CTRL0,0x81); in HDMITX_EnableAudioOutput()
4733 it6161_hdmi_tx_set_bits(it6161, REG_TX_AUDIO_CTRL0,B_TX_AUD_SPDIF, B_TX_AUD_SPDIF); in HDMITX_EnableAudioOutput()
4737 it6161_hdmi_tx_set_bits(it6161, REG_TX_AUDIO_CTRL0, B_TX_AUD_SPDIF, 0x00); in HDMITX_EnableAudioOutput()
4782 it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST,(B_HDMITX_AUD_RST|B_TX_AREF_RST),B_TX_AREF_RST); in HDMITX_EnableAudioOutput()
4793 setHDMITX_ChStat(it6161, pIEC60958ChStat); in HDMITX_EnableAudioOutput()
4804 setHDMITX_ChStat(it6161, pIEC60958ChStat); in HDMITX_EnableAudioOutput()
4811 setHDMITX_ChStat(it6161, pIEC60958ChStat); in HDMITX_EnableAudioOutput()
4816 it6161_hdmi_tx_set_bits(it6161, REG_TX_INT_MASK1, B_TX_AUDIO_OVFLW_MASK, 0x00); in HDMITX_EnableAudioOutput()
4817 it6161_hdmi_tx_write(it6161, REG_TX_AUDIO_CTRL0, hdmiTxDev[0].bAudioChannelEnable); in HDMITX_EnableAudioOutput()
4819 it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST,(B_HDMITX_AUD_RST|B_TX_AREF_RST),0); in HDMITX_EnableAudioOutput()
4830 it6161_hdmi_tx_change_bank(it6161, 0); in hdmitx_AutoAdjustAudio()
4831 it6161_hdmi_tx_write(it6161, 0xF8, 0xC3); in hdmitx_AutoAdjustAudio()
4832 it6161_hdmi_tx_write(it6161, 0xF8, 0xA5); in hdmitx_AutoAdjustAudio()
4833 …it6161_hdmi_tx_set_bits(it6161, REG_TX_PKT_SINGLE_CTRL, B_TX_SW_CTS, 0x00); // D[1] = 0, HW auto c… in hdmitx_AutoAdjustAudio()
4834 it6161_hdmi_tx_write(it6161, 0xF8, 0xFF); in hdmitx_AutoAdjustAudio()
4837 it6161_hdmi_tx_change_bank(it6161, 1); in hdmitx_AutoAdjustAudio()
4838 N = ((u32)it6161_hdmi_tx_read(it6161, REGPktAudN2)&0xF) << 16 ; in hdmitx_AutoAdjustAudio()
4839 N |= ((u32)it6161_hdmi_tx_read(it6161, REGPktAudN1)) <<8 ; in hdmitx_AutoAdjustAudio()
4840 N |= ((u32)it6161_hdmi_tx_read(it6161, REGPktAudN0)); in hdmitx_AutoAdjustAudio()
4844 aCTS = ((u32)it6161_hdmi_tx_read(it6161, REGPktAudCTSCnt2)) << 12 ; in hdmitx_AutoAdjustAudio()
4845 aCTS |= ((u32)it6161_hdmi_tx_read(it6161, REGPktAudCTSCnt1)) <<4 ; in hdmitx_AutoAdjustAudio()
4846 aCTS |= ((u32)it6161_hdmi_tx_read(it6161, REGPktAudCTSCnt0)&0xf0)>>4 ; in hdmitx_AutoAdjustAudio()
4851 it6161_hdmi_tx_change_bank(it6161, 0); in hdmitx_AutoAdjustAudio()
4857 uc = it6161_hdmi_tx_read(it6161, REG_TX_GCP); in hdmitx_AutoAdjustAudio()
4911 it6161_hdmi_tx_change_bank(it6161, 0); in hdmitx_IsAudioChang()
4912 Refaudfreqnum=it6161_hdmi_tx_read(it6161, 0x60); in hdmitx_IsAudioChang()
4918 if((1<<4)&it6161_hdmi_tx_read(it6161, 0x5f)) in hdmitx_IsAudioChang()
4931 it6161_hdmi_tx_set_bits(it6161, REG_TX_PKT_SINGLE_CTRL,(1<<5), (1<<5)); in hdmitx_IsAudioChang()
4932 it6161_hdmi_tx_set_bits(it6161, REG_TX_AUDIO_CTRL0, 0x0F, 0x00); in hdmitx_IsAudioChang()
5022 if(B_TX_HBR & it6161_hdmi_tx_read(it6161, REG_TX_AUD_HDAUDIO)) in setHDMITX_NCTS()
5043 it6161_hdmi_tx_change_bank(it6161, 1); in setHDMITX_NCTS()
5044 it6161_hdmi_tx_write(it6161, REGPktAudN0,(u8)((n)&0xFF)); in setHDMITX_NCTS()
5045 it6161_hdmi_tx_write(it6161, REGPktAudN1,(u8)((n>>8)&0xFF)); in setHDMITX_NCTS()
5046 it6161_hdmi_tx_write(it6161, REGPktAudN2,(u8)((n>>16)&0xF)); in setHDMITX_NCTS()
5054 CTS = ((u32)it6161_hdmi_tx_read(it6161, REGPktAudCTSCnt2)) << 12 ; in setHDMITX_NCTS()
5055 CTS |= ((u32)it6161_hdmi_tx_read(it6161, REGPktAudCTSCnt1)) <<4 ; in setHDMITX_NCTS()
5056 CTS |= ((u32)it6161_hdmi_tx_read(it6161, REGPktAudCTSCnt0)&0xf0)>>4 ; in setHDMITX_NCTS()
5089 it6161_hdmi_tx_write(it6161, REGPktAudCTS0,(u8)((LastCTS)&0xFF)); in setHDMITX_NCTS()
5090 it6161_hdmi_tx_write(it6161, REGPktAudCTS1,(u8)((LastCTS>>8)&0xFF)); in setHDMITX_NCTS()
5091 it6161_hdmi_tx_write(it6161, REGPktAudCTS2,(u8)((LastCTS>>16)&0xF)); in setHDMITX_NCTS()
5092 it6161_hdmi_tx_change_bank(it6161, 0); in setHDMITX_NCTS()
5096 it6161_hdmi_tx_write(it6161, 0xF8, 0xC3); in setHDMITX_NCTS()
5097 it6161_hdmi_tx_write(it6161, 0xF8, 0xA5); in setHDMITX_NCTS()
5100 …it6161_hdmi_tx_set_bits(it6161, REG_TX_PKT_SINGLE_CTRL,B_TX_SW_CTS, B_TX_SW_CTS); // D[1] = 0, HW … in setHDMITX_NCTS()
5104 …it6161_hdmi_tx_set_bits(it6161, REG_TX_PKT_SINGLE_CTRL, B_TX_SW_CTS, 0x00); // D[1] = 0, HW auto c… in setHDMITX_NCTS()
5106 it6161_hdmi_tx_write(it6161, 0xF8, 0xFF); in setHDMITX_NCTS()
5111 it6161_hdmi_tx_change_bank(it6161, 1); in setHDMITX_NCTS()
5113 it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_CA_FS,0x00|Fs); in setHDMITX_NCTS()
5115 uData = (0x0f&it6161_hdmi_tx_read(it6161, REG_TX_AUDCHST_OFS_WL)); in setHDMITX_NCTS()
5116 it6161_hdmi_tx_write(it6161, REG_TX_AUDCHST_OFS_WL,(Fs<<4)|uData); in setHDMITX_NCTS()
5117 it6161_hdmi_tx_change_bank(it6161, 0); in setHDMITX_NCTS()
5130 static SYS_STATUS hdmitx_SetAudioInfoFrame(struct it6161 *it6161, Audio_InfoFrame *pAudioInfoFrame) in hdmitx_SetAudioInfoFrame() argument
5138 it6161_hdmi_tx_change_bank(it6161, 1); in hdmitx_SetAudioInfoFrame()
5140 it6161_hdmi_tx_write(it6161, REG_TX_PKT_AUDINFO_CC,pAudioInfoFrame->pktbyte.AUD_DB[0]); in hdmitx_SetAudioInfoFrame()
5141 checksum -= it6161_hdmi_tx_read(it6161, REG_TX_PKT_AUDINFO_CC); checksum &= 0xFF ; in hdmitx_SetAudioInfoFrame()
5142 it6161_hdmi_tx_write(it6161, REG_TX_PKT_AUDINFO_SF,pAudioInfoFrame->pktbyte.AUD_DB[1]); in hdmitx_SetAudioInfoFrame()
5143 checksum -= it6161_hdmi_tx_read(it6161, REG_TX_PKT_AUDINFO_SF); checksum &= 0xFF ; in hdmitx_SetAudioInfoFrame()
5144 it6161_hdmi_tx_write(it6161, REG_TX_PKT_AUDINFO_CA,pAudioInfoFrame->pktbyte.AUD_DB[3]); in hdmitx_SetAudioInfoFrame()
5145 checksum -= it6161_hdmi_tx_read(it6161, REG_TX_PKT_AUDINFO_CA); checksum &= 0xFF ; in hdmitx_SetAudioInfoFrame()
5146 it6161_hdmi_tx_write(it6161, REG_TX_PKT_AUDINFO_DM_LSV,pAudioInfoFrame->pktbyte.AUD_DB[4]); in hdmitx_SetAudioInfoFrame()
5147 checksum -= it6161_hdmi_tx_read(it6161, REG_TX_PKT_AUDINFO_DM_LSV); checksum &= 0xFF ; in hdmitx_SetAudioInfoFrame()
5149 it6161_hdmi_tx_write(it6161, REG_TX_PKT_AUDINFO_SUM,checksum); in hdmitx_SetAudioInfoFrame()
5151 it6161_hdmi_tx_change_bank(it6161, 0); in hdmitx_SetAudioInfoFrame()
5165 static SYS_STATUS hdmitx_SetAVIInfoFrame(struct it6161 *it6161, AVI_InfoFrame *pAVIInfoFrame)
5174 it6161_hdmi_tx_change_bank(it6161, 1);
5175 it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB1,pAVIInfoFrame->pktbyte.AVI_DB[0]);
5176 it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB2,pAVIInfoFrame->pktbyte.AVI_DB[1]);
5177 it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB3,pAVIInfoFrame->pktbyte.AVI_DB[2]);
5178 it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB4,pAVIInfoFrame->pktbyte.AVI_DB[3]);
5179 it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB5,pAVIInfoFrame->pktbyte.AVI_DB[4]);
5180 it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB6,pAVIInfoFrame->pktbyte.AVI_DB[5]);
5181 it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB7,pAVIInfoFrame->pktbyte.AVI_DB[6]);
5182 it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB8,pAVIInfoFrame->pktbyte.AVI_DB[7]);
5183 it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB9,pAVIInfoFrame->pktbyte.AVI_DB[8]);
5184 it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB10,pAVIInfoFrame->pktbyte.AVI_DB[9]);
5185 it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB11,pAVIInfoFrame->pktbyte.AVI_DB[10]);
5186 it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB12,pAVIInfoFrame->pktbyte.AVI_DB[11]);
5187 it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB13,pAVIInfoFrame->pktbyte.AVI_DB[12]);
5210 it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_SUM,checksum);
5212 it6161_hdmi_tx_change_bank(it6161, 0);
5217 static SYS_STATUS hdmitx_SetVSIInfoFrame(struct it6161 *it6161, VendorSpecific_InfoFrame *pVSIInfoF… in hdmitx_SetVSIInfoFrame() argument
5226 it6161_hdmi_tx_change_bank(it6161, 1); in hdmitx_SetVSIInfoFrame()
5227 it6161_hdmi_tx_write(it6161, 0x80,pVSIInfoFrame->pktbyte.VS_DB[3]); in hdmitx_SetVSIInfoFrame()
5228 it6161_hdmi_tx_write(it6161, 0x81,pVSIInfoFrame->pktbyte.VS_DB[4]); in hdmitx_SetVSIInfoFrame()
5236 it6161_hdmi_tx_write(it6161, 0x82,pVSIInfoFrame->pktbyte.VS_DB[5]); in hdmitx_SetVSIInfoFrame()
5246 it6161_hdmi_tx_write(it6161, 0x83,pVSIInfoFrame->pktbyte.CheckSum); in hdmitx_SetVSIInfoFrame()
5247 it6161_hdmi_tx_change_bank(it6161, 0); in hdmitx_SetVSIInfoFrame()
5248 it6161_hdmi_tx_write(it6161, REG_TX_3D_INFO_CTRL,B_TX_ENABLE_PKT|B_TX_REPEAT_PKT); in hdmitx_SetVSIInfoFrame()
5252 static bool HDMITX_EnableVSInfoFrame(struct it6161 *it6161, u8 bEnable,u8 *pVSInfoFrame) in HDMITX_EnableVSInfoFrame() argument
5259 if(hdmitx_SetVSIInfoFrame(it6161, (VendorSpecific_InfoFrame *)pVSInfoFrame) == ER_SUCCESS) in HDMITX_EnableVSInfoFrame()
5280 static bool HDMITX_EnableAudioInfoFrame(struct it6161 *it6161, u8 bEnable,u8 *pAudioInfoFrame) in HDMITX_EnableAudioInfoFrame() argument
5287 if(hdmitx_SetAudioInfoFrame(it6161, (Audio_InfoFrame *)pAudioInfoFrame) == ER_SUCCESS) in HDMITX_EnableAudioInfoFrame()
5432 static void ConfigAudioInfoFrm(struct it6161 *it6161, u8 channel_count) in ConfigAudioInfoFrm() argument
5479 HDMITX_EnableAudioInfoFrame(it6161, TRUE, (unsigned char *)AudioInfo); in ConfigAudioInfoFrm()
5483 void ConfigfHdmiVendorSpecificInfoFrame(struct it6161 *it6161, u8 _3D_Stru) in ConfigfHdmiVendorSpecificInfoFrame() argument
5508 HDMITX_EnableVSInfoFrame(it6161, true,(u8 *)VS_Info); in ConfigfHdmiVendorSpecificInfoFrame()
5512 static void hdmi_tx_audio_process(struct it6161 *it6161) in hdmi_tx_audio_process() argument
5514 if (it6161->support_audio) { in hdmi_tx_audio_process()
5515 ConfigAudioInfoFrm(it6161, bOutputAudioChannel); in hdmi_tx_audio_process()
5517 HDMITX_EnableAudioOutput(it6161, in hdmi_tx_audio_process()
5551 static int hdmi_tx_get_avi_infoframe_from_source(struct it6161 *it6161, u8 *buffer, size_t size) in hdmi_tx_get_avi_infoframe_from_source() argument
5553 struct device *dev = &it6161->i2c_mipi_rx->dev; in hdmi_tx_get_avi_infoframe_from_source()
5556 err = hdmi_avi_infoframe_pack(&it6161->source_avi_infoframe, buffer, size); in hdmi_tx_get_avi_infoframe_from_source()
5565 static int hdmi_tx_get_avi_infoframe_from_user_define(struct it6161 *it6161, u8 *buffer, size_t siz… in hdmi_tx_get_avi_infoframe_from_user_define() argument
5567 struct device *dev = &it6161->i2c_hdmi_tx->dev; in hdmi_tx_get_avi_infoframe_from_user_define()
5568 struct hdmi_avi_infoframe *frame = &it6161->source_avi_infoframe; in hdmi_tx_get_avi_infoframe_from_user_define()
5569 struct drm_display_mode *display_mode = &it6161->source_display_mode; in hdmi_tx_get_avi_infoframe_from_user_define()
5574 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, &it6161->connector, display_mode); in hdmi_tx_get_avi_infoframe_from_user_define()
5580 if ((it6161->hdmi_tx_output_color_space & F_MODE_CLRMOD_MASK) == F_MODE_RGB444) in hdmi_tx_get_avi_infoframe_from_user_define()
5583 if ((it6161->hdmi_tx_output_color_space & F_MODE_CLRMOD_MASK) == F_MODE_YUV444) in hdmi_tx_get_avi_infoframe_from_user_define()
5586 if ((it6161->hdmi_tx_output_color_space & F_MODE_CLRMOD_MASK) == F_MODE_YUV422) in hdmi_tx_get_avi_infoframe_from_user_define()
5589 ret = hdmi_tx_get_avi_infoframe_from_source(it6161, buffer, size); in hdmi_tx_get_avi_infoframe_from_user_define()
5598 static int (*hdmi_tx_get_avi_infoframe)(struct it6161*, u8*, size_t) = hdmi_tx_get_avi_infoframe_fr…
5600 static void hdmi_tx_setup_avi_infoframe(struct it6161 *it6161, u8 *buffer, size_t size) in hdmi_tx_setup_avi_infoframe() argument
5604 it6161_hdmi_tx_change_bank(it6161, 1); in hdmi_tx_setup_avi_infoframe()
5606 for (i = 0; i < it6161->source_avi_infoframe.length; i++) in hdmi_tx_setup_avi_infoframe()
5607 it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_DB1 + i, ptr[i]); in hdmi_tx_setup_avi_infoframe()
5609 it6161_hdmi_tx_write(it6161, REG_TX_AVIINFO_SUM, buffer[3]); in hdmi_tx_setup_avi_infoframe()
5612 static inline void hdmi_tx_disable_avi_infoframe(struct it6161 *it6161) in hdmi_tx_disable_avi_infoframe() argument
5614 it6161_hdmi_tx_change_bank(it6161, 0); in hdmi_tx_disable_avi_infoframe()
5615 it6161_hdmi_tx_write(it6161, REG_TX_AVI_INFOFRM_CTRL, 0x00); in hdmi_tx_disable_avi_infoframe()
5618 static inline void hdmi_tx_enable_avi_infoframe(struct it6161 *it6161) in hdmi_tx_enable_avi_infoframe() argument
5620 it6161_hdmi_tx_change_bank(it6161, 0); in hdmi_tx_enable_avi_infoframe()
5621 it6161_hdmi_tx_write(it6161, REG_TX_AVI_INFOFRM_CTRL, B_TX_ENABLE_PKT | B_TX_REPEAT_PKT); in hdmi_tx_enable_avi_infoframe()
5624 static int hdmi_tx_avi_infoframe_process(struct it6161 *it6161) in hdmi_tx_avi_infoframe_process() argument
5629 hdmi_tx_disable_avi_infoframe(it6161); in hdmi_tx_avi_infoframe_process()
5630 err = hdmi_tx_get_avi_infoframe(it6161, buffer, sizeof(buffer)); in hdmi_tx_avi_infoframe_process()
5635 hdmi_tx_setup_avi_infoframe(it6161, buffer, sizeof(buffer)); in hdmi_tx_avi_infoframe_process()
5636 hdmi_tx_enable_avi_infoframe(it6161); in hdmi_tx_avi_infoframe_process()
5643 static void hdmi_tx_set_output_process(struct it6161 *it6161) in hdmi_tx_set_output_process() argument
5648 TMDSClock = it6161->hdmi_tx_pclk * 1000 * (it6161->source_avi_infoframe.pixel_repeat + 1); in hdmi_tx_set_output_process()
5650 HDMITX_DisableAudioOutput(it6161); in hdmi_tx_set_output_process()
5652 hdmi_tx_disable_avi_infoframe(it6161); in hdmi_tx_set_output_process()
5653 HDMITX_EnableVSInfoFrame(it6161, false,NULL); in hdmi_tx_set_output_process()
5663 hdmi_tx_enable_video_output(it6161, level); in hdmi_tx_set_output_process()
5665 if (it6161->hdmi_mode) { in hdmi_tx_set_output_process()
5667 ConfigfHdmiVendorSpecificInfoFrame(it6161, OUTPUT_3D_MODE); in hdmi_tx_set_output_process()
5670 hdmi_tx_avi_infoframe_process(it6161); in hdmi_tx_set_output_process()
5671 hdmi_tx_audio_process(it6161); in hdmi_tx_set_output_process()
5687 it6161_hdmi_tx_change_bank(it6161, 0); in hdmi_tx_set_output_process()
5688 it6161_hdmi_tx_write(it6161, 0xf, 0 ); in hdmi_tx_set_output_process()
5692 it6161_hdmi_tx_set_av_mute(it6161, false); in hdmi_tx_set_output_process()
5771 if( !it6161->support_audio ) in HDMITX_MonitorInputAudioChange()
5813 ConfigAudioInfoFrm(it6161, 2); in HDMITX_MonitorInputAudioChange()
5814 …HDMITX_EnableAudioOutput(it6161, CNOFIG_INPUT_AUDIO_TYPE, CONFIG_INPUT_AUDIO_INTERFACE, ulAudioSam… in HDMITX_MonitorInputAudioChange()
5827 static void mipi_rx_calc_rclk(struct it6161 *it6161) in mipi_rx_calc_rclk() argument
5834 it6161_mipi_rx_set_bits(it6161, 0x94, 0x80, 0x80); // Enable RCLK 100ms count in mipi_rx_calc_rclk()
5836 it6161_mipi_rx_set_bits(it6161, 0x94, 0x80, 0x00); // Disable RCLK 100ms count in mipi_rx_calc_rclk()
5838 it6161->mipi_rx_rclk = it6161_mipi_rx_read(it6161, 0x97); in mipi_rx_calc_rclk()
5839 it6161->mipi_rx_rclk <<= 8; in mipi_rx_calc_rclk()
5840 it6161->mipi_rx_rclk += it6161_mipi_rx_read(it6161, 0x96); in mipi_rx_calc_rclk()
5841 it6161->mipi_rx_rclk <<=8; in mipi_rx_calc_rclk()
5842 it6161->mipi_rx_rclk += it6161_mipi_rx_read(it6161, 0x95); in mipi_rx_calc_rclk()
5843 sum += it6161->mipi_rx_rclk; in mipi_rx_calc_rclk()
5849 it6161->mipi_rx_rclk = sum / 104; in mipi_rx_calc_rclk()
5850 t10usint = it6161->mipi_rx_rclk / 108;//actually nxp platform msleep(100) is 108ms in mipi_rx_calc_rclk()
5853 it6161_mipi_rx_write(it6161, 0x91, t10usint&0xFF); in mipi_rx_calc_rclk()
5856 static void mipi_rx_calc_mclk(struct it6161 *it6161) in mipi_rx_calc_mclk() argument
5861 it6161_mipi_rx_set_bits(it6161, 0x9B, 0x80, 0x80); in mipi_rx_calc_mclk()
5863 it6161_mipi_rx_set_bits(it6161, 0x9B, 0x80, 0x00); in mipi_rx_calc_mclk()
5865 rddata = it6161_mipi_rx_read(it6161, 0x9B) & 0x0F; in mipi_rx_calc_mclk()
5867 rddata += it6161_mipi_rx_read(it6161, 0x9A); in mipi_rx_calc_mclk()
5873 it6161->mipi_rx_mclk = it6161->mipi_rx_rclk * 2048 / sum; in mipi_rx_calc_mclk()
5874 DRM_INFO("MCLK = %d.%03dMHz", it6161->mipi_rx_mclk / 1000, it6161->mipi_rx_mclk % 1000); in mipi_rx_calc_mclk()
5877 static void mipi_rx_calc_pclk(struct it6161 *it6161) in mipi_rx_calc_pclk() argument
5882 it6161_mipi_rx_set_bits(it6161, 0x99, 0x80, 0x00); in mipi_rx_calc_pclk()
5885 it6161_mipi_rx_set_bits(it6161, 0x99, 0x80, 0x80); in mipi_rx_calc_pclk()
5887 it6161_mipi_rx_set_bits(it6161, 0x99, 0x80, 0x00); in mipi_rx_calc_pclk()
5890 rddata = it6161_mipi_rx_read(it6161, 0x99) & 0x0F; in mipi_rx_calc_pclk()
5892 rddata += it6161_mipi_rx_read(it6161, 0x98); in mipi_rx_calc_pclk()
5898 it6161->mipi_rx_pclk = it6161->mipi_rx_rclk * 2048 / sum; in mipi_rx_calc_pclk()
5900 …DRM_INFO("it6161->mipi_rx_pclk = %d.%03dMHz", it6161->mipi_rx_pclk / 1000, it6161->mipi_rx_pclk % … in mipi_rx_calc_pclk()
5903 static void mipi_rx_show_mrec(struct it6161 *it6161) in mipi_rx_show_mrec() argument
5909 m_hfront_porch = mipi_rx_read_word(it6161, 0x50) & 0x3FFF; in mipi_rx_show_mrec()
5910 m_hsyncw = mipi_rx_read_word(it6161, 0x52) & 0x3FFF; in mipi_rx_show_mrec()
5911 m_hback_porch = mipi_rx_read_word(it6161, 0x54) & 0x3FFF; in mipi_rx_show_mrec()
5912 m_hactive = mipi_rx_read_word(it6161, 0x56) & 0x3FFF; in mipi_rx_show_mrec()
5913 MHVR2nd = mipi_rx_read_word(it6161, 0x58) & 0x3FFF; in mipi_rx_show_mrec()
5917 m_vfront_porch = mipi_rx_read_word(it6161, 0x5A) & 0x3FFF; in mipi_rx_show_mrec()
5918 m_vsyncw = mipi_rx_read_word(it6161, 0x5C) & 0x3FFF; in mipi_rx_show_mrec()
5919 m_vback_porch = mipi_rx_read_word(it6161, 0x5E) & 0x3FFF; in mipi_rx_show_mrec()
5920 m_vactive = mipi_rx_read_word(it6161, 0x60) & 0x3FFF; in mipi_rx_show_mrec()
5921 MVFP2nd = mipi_rx_read_word(it6161, 0x62) & 0x3FFF; in mipi_rx_show_mrec()
5940 static void mipi_rx_prec_get_display_mode(struct it6161 *it6161) in mipi_rx_prec_get_display_mode() argument
5942 struct drm_display_mode *display_mode = &it6161->mipi_rx_p_display_mode; in mipi_rx_prec_get_display_mode()
5943 struct device *dev = &it6161->i2c_hdmi_tx->dev; in mipi_rx_prec_get_display_mode()
5947 p_hfront_porch = mipi_rx_read_word(it6161, 0x30) & 0x3FFF; in mipi_rx_prec_get_display_mode()
5948 p_hsyncw = mipi_rx_read_word(it6161, 0x32) & 0x3FFF; in mipi_rx_prec_get_display_mode()
5949 p_hback_porch = mipi_rx_read_word(it6161, 0x34) & 0x3FFF; in mipi_rx_prec_get_display_mode()
5950 p_hactive = mipi_rx_read_word(it6161, 0x36) & 0x3FFF; in mipi_rx_prec_get_display_mode()
5951 p_htotal = mipi_rx_read_word(it6161, 0x38) & 0x3FFF; in mipi_rx_prec_get_display_mode()
5955 p_vfront_porch = mipi_rx_read_word(it6161, 0x3A) & 0x3FFF; in mipi_rx_prec_get_display_mode()
5956 p_vsyncw = mipi_rx_read_word(it6161, 0x3C) & 0x3FFF; in mipi_rx_prec_get_display_mode()
5957 p_vback_porch = mipi_rx_read_word(it6161, 0x3E) & 0x3FFF; in mipi_rx_prec_get_display_mode()
5958 p_vactive = mipi_rx_read_word(it6161, 0x40) & 0x3FFF; in mipi_rx_prec_get_display_mode()
5959 p_vtotal = mipi_rx_read_word(it6161, 0x42) & 0x3FFF; in mipi_rx_prec_get_display_mode()
5963 display_mode->clock = it6161->mipi_rx_pclk; in mipi_rx_prec_get_display_mode()
5987 static void mipi_rx_reset_p_domain(struct it6161 *it6161) in mipi_rx_reset_p_domain() argument
5989 it6161_mipi_rx_set_bits(it6161, 0x05, 0x04, 0x04); // Video Clock Domain Reset in mipi_rx_reset_p_domain()
5990 it6161_mipi_rx_set_bits(it6161, 0x05, 0x04, 0x00); // Release Video Clock Domain Reset in mipi_rx_reset_p_domain()
5993 static void it6161_mipi_rx_interrupt_clear(struct it6161 *it6161, u8 reg06, u8 reg07, u8 reg08) in it6161_mipi_rx_interrupt_clear() argument
5995 it6161_mipi_rx_write(it6161, 0x06, reg06); in it6161_mipi_rx_interrupt_clear()
5996 it6161_mipi_rx_write(it6161, 0x07, reg07); in it6161_mipi_rx_interrupt_clear()
5997 it6161_mipi_rx_write(it6161, 0x08, reg08); in it6161_mipi_rx_interrupt_clear()
5999 …it6161_mipi_rx_read(it6161, 0x06), it6161_mipi_rx_read(it6161, 0x07), it6161_mipi_rx_read(it6161, … in it6161_mipi_rx_interrupt_clear()
6002 static void it6161_mipi_rx_interrupt_reg06_process(struct it6161 *it6161, u8 reg06) in it6161_mipi_rx_interrupt_reg06_process() argument
6014 m_video_stable = mipi_rx_get_m_video_stable(it6161); in it6161_mipi_rx_interrupt_reg06_process()
6018 data_id = it6161_mipi_rx_read(it6161, 0x28); in it6161_mipi_rx_interrupt_reg06_process()
6020 mipi_rx_calc_rclk(it6161); in it6161_mipi_rx_interrupt_reg06_process()
6021 mipi_rx_calc_mclk(it6161); in it6161_mipi_rx_interrupt_reg06_process()
6022 mipi_rx_show_mrec(it6161); in it6161_mipi_rx_interrupt_reg06_process()
6023 mipi_rx_afe_configuration(it6161, data_id); in it6161_mipi_rx_interrupt_reg06_process()
6024 mipi_rx_reset_p_domain(it6161); in it6161_mipi_rx_interrupt_reg06_process()
6044 p_video_stable = mipi_rx_get_p_video_stable(it6161); in it6161_mipi_rx_interrupt_reg06_process()
6047 cancel_delayed_work(&it6161->restart); in it6161_mipi_rx_interrupt_reg06_process()
6051 mipi_rx_calc_rclk(it6161); in it6161_mipi_rx_interrupt_reg06_process()
6052 mipi_rx_calc_pclk(it6161); in it6161_mipi_rx_interrupt_reg06_process()
6053 mipi_rx_prec_get_display_mode(it6161); in it6161_mipi_rx_interrupt_reg06_process()
6054 it6161->vic = drm_match_cea_mode(&it6161->mipi_rx_p_display_mode); in it6161_mipi_rx_interrupt_reg06_process()
6057 if (it6161->vic == 0) { in it6161_mipi_rx_interrupt_reg06_process()
6058 dmt_display_mode = drm_match_dmt_mode(&it6161->mipi_rx_p_display_mode); in it6161_mipi_rx_interrupt_reg06_process()
6061 it6161->source_display_mode = *dmt_display_mode; in it6161_mipi_rx_interrupt_reg06_process()
6065 it6161->source_display_mode = edid_cea_modes[it6161->vic]; in it6161_mipi_rx_interrupt_reg06_process()
6069 … DRM_INFO("source output vic: %d, %s cea timing", it6161->vic, it6161->vic ? " standard" : " not"); in it6161_mipi_rx_interrupt_reg06_process()
6070 show_display_mode(it6161, &it6161->source_display_mode, 0); in it6161_mipi_rx_interrupt_reg06_process()
6072 show_display_mode(it6161, &it6161->mipi_rx_p_display_mode, 2); in it6161_mipi_rx_interrupt_reg06_process()
6073 mipi_rx_setup_polarity(it6161); in it6161_mipi_rx_interrupt_reg06_process()
6074 it6161_mipi_rx_write(it6161, 0xC0,(EnTxCRC<<7) +TxCRCnum); in it6161_mipi_rx_interrupt_reg06_process()
6076 it6161_mipi_rx_set_bits(it6161, 0x0b,0x40, 0x40); in it6161_mipi_rx_interrupt_reg06_process()
6078 switch (it6161->hdmi_tx_mode) { in it6161_mipi_rx_interrupt_reg06_process()
6080 it6161_hdmi_tx_set_bits(it6161, 0xA9, 0x80, 0x80); in it6161_mipi_rx_interrupt_reg06_process()
6084 hdmi_tx_generate_blank_timing(it6161); in it6161_mipi_rx_interrupt_reg06_process()
6088 hdmi_tx_setup_pattern_generator(it6161); in it6161_mipi_rx_interrupt_reg06_process()
6096 hdmi_tx_video_reset(it6161); in it6161_mipi_rx_interrupt_reg06_process()
6119 static void it6161_mipi_rx_interrupt_reg07_process(struct it6161 *it6161, u8 reg07) in it6161_mipi_rx_interrupt_reg07_process() argument
6157 … DRM_INFO("PPS FIFO over read Interrupt !!! tx video stable:%d", hdmi_tx_get_video_state(it6161)); in it6161_mipi_rx_interrupt_reg07_process()
6158 it6161_mipi_rx_set_bits(it6161, 0x07, 0x40, 0x40); in it6161_mipi_rx_interrupt_reg07_process()
6162 it6161_mipi_rx_set_bits(it6161, 0x07, 0x80, 0x80); in it6161_mipi_rx_interrupt_reg07_process()
6167 static void it6161_mipi_rx_interrupt_reg08_process(struct it6161 *it6161, u8 reg08) in it6161_mipi_rx_interrupt_reg08_process() argument
6215 it6161_mipi_rx_set_bits(it6161, 0x0b, 0x40, 0x00); in it6161_mipi_rx_interrupt_reg08_process()
6217 if((it6161_mipi_rx_read(it6161, 0xC1)&0x03) == 0x03) in it6161_mipi_rx_interrupt_reg08_process()
6221 if((it6161_mipi_rx_read(it6161, 0xC1)&0x05) == 0x05) in it6161_mipi_rx_interrupt_reg08_process()
6224 crc = it6161_mipi_rx_read(it6161, 0xC2) + (it6161_mipi_rx_read(it6161, 0xC3) <<8); in it6161_mipi_rx_interrupt_reg08_process()
6226 crc = it6161_mipi_rx_read(it6161, 0xC4) + (it6161_mipi_rx_read(it6161, 0xC5) <<8); in it6161_mipi_rx_interrupt_reg08_process()
6228 crc = it6161_mipi_rx_read(it6161, 0xC6) + (it6161_mipi_rx_read(it6161, 0xC7) <<8); in it6161_mipi_rx_interrupt_reg08_process()
6234 static void it6161_hdmi_tx_interrupt_clear(struct it6161 *it6161, u8 reg06, u8 reg07, u8 reg08, u8 … in it6161_hdmi_tx_interrupt_clear() argument
6240 …it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST,(B_HDMITX_AUD_RST|B_TX_AREF_RST), (B_HDMITX_AUD_RST|… in it6161_hdmi_tx_interrupt_clear()
6241 it6161_hdmi_tx_set_bits(it6161, REG_TX_SW_RST, B_HDMITX_AUD_RST|B_TX_AREF_RST, 0x00); in it6161_hdmi_tx_interrupt_clear()
6248 it6161_hdmi_tx_clear_ddc_fifo(it6161); in it6161_hdmi_tx_interrupt_clear()
6254 it6161_hdmi_tx_abort_ddc(it6161); in it6161_hdmi_tx_interrupt_clear()
6260 hdmitx_hdcp_ResumeAuthentication(it6161); in it6161_hdmi_tx_interrupt_clear()
6269 it6161_hdmi_tx_write(it6161, 0xEE, regee); in it6161_hdmi_tx_interrupt_clear()
6270 it6161_hdmi_tx_write(it6161, REG_TX_INT_CLR0, 0xFF); in it6161_hdmi_tx_interrupt_clear()
6271 it6161_hdmi_tx_write(it6161, REG_TX_INT_CLR1, 0xFF); in it6161_hdmi_tx_interrupt_clear()
6273 int_clear = (it6161_hdmi_tx_read(it6161, REG_TX_SYS_STATUS)) | B_TX_CLR_AUD_CTS | B_TX_INTACTDONE ; in it6161_hdmi_tx_interrupt_clear()
6274 it6161_hdmi_tx_write(it6161, REG_TX_SYS_STATUS, int_clear); in it6161_hdmi_tx_interrupt_clear()
6276 … it6161_hdmi_tx_read(it6161, 0x06), it6161_hdmi_tx_read(it6161, 0x07), it6161_hdmi_tx_read(it6161,… in it6161_hdmi_tx_interrupt_clear()
6279 static void it6161_hdmi_tx_interrupt_reg06_process(struct it6161 *it6161, u8 reg06) in it6161_hdmi_tx_interrupt_reg06_process() argument
6285 drm_helper_hpd_irq_event(it6161->connector.dev); in it6161_hdmi_tx_interrupt_reg06_process()
6286 if(hdmi_tx_get_sink_hpd(it6161)) { in it6161_hdmi_tx_interrupt_reg06_process()
6288 ret = wait_for_completion_timeout(&it6161->wait_edid_complete, msecs_to_jiffies(2000)); in it6161_hdmi_tx_interrupt_reg06_process()
6293 it6161->hdmi_tx_output_color_space = OUTPUT_COLOR_MODE; in it6161_hdmi_tx_interrupt_reg06_process()
6294 it6161->hdmi_tx_input_color_space = INPUT_COLOR_MODE; in it6161_hdmi_tx_interrupt_reg06_process()
6295 hdmi_tx_set_capability_from_edid_parse(it6161); in it6161_hdmi_tx_interrupt_reg06_process()
6296 reinit_completion(&it6161->wait_hdcp_event); in it6161_hdmi_tx_interrupt_reg06_process()
6297 hdmi_tx_video_reset(it6161); in it6161_hdmi_tx_interrupt_reg06_process()
6304 hdmi_tx_disable_video_output(it6161); in it6161_hdmi_tx_interrupt_reg06_process()
6305 kfree(it6161->edid); in it6161_hdmi_tx_interrupt_reg06_process()
6306 it6161->edid = NULL; in it6161_hdmi_tx_interrupt_reg06_process()
6308 if (it6161->hdmi_tx_mode == HDMI_TX_ENABLE_PATTERN_GENERATOR) in it6161_hdmi_tx_interrupt_reg06_process()
6309 hdmi_tx_disable_pattern_generator(it6161); in it6161_hdmi_tx_interrupt_reg06_process()
6319 static void it6161_hdmi_tx_interrupt_reg07_process(struct it6161 *it6161, u8 reg07) in it6161_hdmi_tx_interrupt_reg07_process() argument
6321 bool video_state = hdmi_tx_get_video_state(it6161); in it6161_hdmi_tx_interrupt_reg07_process()
6325 hdmi_tx_hdcp_int_mask_disable(it6161); in it6161_hdmi_tx_interrupt_reg07_process()
6327 it6161_hdmi_tx_set_av_mute(it6161, false); in it6161_hdmi_tx_interrupt_reg07_process()
6328 complete(&it6161->wait_hdcp_event); in it6161_hdmi_tx_interrupt_reg07_process()
6332 …tx interrupt authenticate fail reg46:0x%02x, start HDCP again", it6161_hdmi_tx_read(it6161, 0x46)); in it6161_hdmi_tx_interrupt_reg07_process()
6333 complete(&it6161->wait_hdcp_event); in it6161_hdmi_tx_interrupt_reg07_process()
6335 hdmi_tx_enable_hdcp(it6161); in it6161_hdmi_tx_interrupt_reg07_process()
6344 schedule_work(&it6161->wait_hdcp_ksv_list); in it6161_hdmi_tx_interrupt_reg07_process()
6353 static void it6161_hdmi_tx_interrupt_reg08_process(struct it6161 *it6161, u8 reg08) in it6161_hdmi_tx_interrupt_reg08_process() argument
6356 it6161_hdmi_tx_write(it6161, REG_TX_INT_STAT3, reg08); in it6161_hdmi_tx_interrupt_reg08_process()
6357 if (hdmi_tx_get_video_state(it6161)) { in it6161_hdmi_tx_interrupt_reg08_process()
6358 …status:%d, rx reg0d:0x%02x start HDCP", getHDMITX_LinkStatus(), it6161_mipi_rx_read(it6161, 0x0D)); in it6161_hdmi_tx_interrupt_reg08_process()
6359 hdmi_tx_get_display_mode(it6161); in it6161_hdmi_tx_interrupt_reg08_process()
6360 show_display_mode(it6161, &it6161->source_display_mode, 0); in it6161_hdmi_tx_interrupt_reg08_process()
6361 show_display_mode(it6161, &it6161->hdmi_tx_display_mode, 1); in it6161_hdmi_tx_interrupt_reg08_process()
6362 hdmi_tx_set_output_process(it6161); in it6161_hdmi_tx_interrupt_reg08_process()
6364 hdmi_tx_enable_hdcp(it6161); in it6161_hdmi_tx_interrupt_reg08_process()
6370 static void it6161_hdmi_tx_interrupt_regee_process(struct it6161 *it6161, u8 regee) in it6161_hdmi_tx_interrupt_regee_process() argument
6386 struct it6161 *it6161 = data; in it6161_intp_threaded_handler() local
6392 if (it6161->enable_drv_hold) in it6161_intp_threaded_handler()
6395 mipi_rx_reg06 = it6161_mipi_rx_read(it6161, 0x06); in it6161_intp_threaded_handler()
6396 mipi_rx_reg07 = it6161_mipi_rx_read(it6161, 0x07); in it6161_intp_threaded_handler()
6397 mipi_rx_reg08 = it6161_mipi_rx_read(it6161, 0x08); in it6161_intp_threaded_handler()
6398 mipi_rx_reg0d = it6161_mipi_rx_read(it6161, 0x0D); in it6161_intp_threaded_handler()
6400 hdmi_tx_reg06 = it6161_hdmi_tx_read(it6161, 0x06); in it6161_intp_threaded_handler()
6401 hdmi_tx_reg07 = it6161_hdmi_tx_read(it6161, 0x07); in it6161_intp_threaded_handler()
6402 hdmi_tx_reg08 = it6161_hdmi_tx_read(it6161, 0x08); in it6161_intp_threaded_handler()
6403 hdmi_tx_reg0e = it6161_hdmi_tx_read(it6161, 0x0E); in it6161_intp_threaded_handler()
6404 hdmi_tx_regee = it6161_hdmi_tx_read(it6161, 0xEE); in it6161_intp_threaded_handler()
6408 it6161_mipi_rx_interrupt_clear(it6161, mipi_rx_reg06, mipi_rx_reg07, mipi_rx_reg08); in it6161_intp_threaded_handler()
6413 …it6161_hdmi_tx_interrupt_clear(it6161, hdmi_tx_reg06, hdmi_tx_reg07, hdmi_tx_reg08, hdmi_tx_regee); in it6161_intp_threaded_handler()
6416 it6161_mipi_rx_interrupt_reg08_process(it6161, mipi_rx_reg08); in it6161_intp_threaded_handler()
6417 it6161_mipi_rx_interrupt_reg06_process(it6161, mipi_rx_reg06); in it6161_intp_threaded_handler()
6418 it6161_mipi_rx_interrupt_reg07_process(it6161, mipi_rx_reg07); in it6161_intp_threaded_handler()
6419 it6161_hdmi_tx_interrupt_reg06_process(it6161, hdmi_tx_reg06); in it6161_intp_threaded_handler()
6420 it6161_hdmi_tx_interrupt_reg07_process(it6161, hdmi_tx_reg07); in it6161_intp_threaded_handler()
6421 it6161_hdmi_tx_interrupt_reg08_process(it6161, hdmi_tx_reg08); in it6161_intp_threaded_handler()
6422 it6161_hdmi_tx_interrupt_regee_process(it6161, hdmi_tx_regee); in it6161_intp_threaded_handler()
6439 struct it6161 *it6161 = dev_get_drvdata(dev);
6441 return scnprintf(buf, PAGE_SIZE, "drv_hold: %d\n", it6161->enable_drv_hold);
6448 struct it6161 *it6161 = dev_get_drvdata(dev);
6454 it6161->enable_drv_hold = !!drv_hold;
6456 if (it6161->enable_drv_hold) {
6457 it6161_mipi_rx_int_mask_disable(it6161);
6458 it6161_hdmi_tx_int_mask_disable(it6161);
6460 it6161_mipi_rx_interrupt_clear(it6161, 0xFF, 0xFF, 0xFF);
6461 it6161_hdmi_tx_interrupt_clear(it6161, 0xFF, 0xFF, 0xFF, 0xFF);
6462 it6161_mipi_rx_int_mask_enable(it6161);
6463 it6161_hdmi_tx_int_mask_enable(it6161);
6472 struct it6161 *it6161 = dev_get_drvdata(dev);
6475 it6161->hdmi_tx_output_color_space &= ~F_MODE_CLRMOD_MASK;
6478 it6161->hdmi_tx_output_color_space |= F_MODE_YUV444;
6483 it6161->hdmi_tx_output_color_space |= F_MODE_YUV422;
6488 it6161->hdmi_tx_output_color_space |= F_MODE_RGB444;
6496 DRM_INFO("config color space: %s value:0x%02x", buf, it6161->hdmi_tx_output_color_space);
6503 struct it6161 *it6161 = dev_get_drvdata(dev);
6506 …str += scnprintf(str, end - str, "it6161->hdmi_tx_output_color_space:%d\n", it6161->hdmi_tx_output…
6516 struct it6161 *it6161 = dev_get_drvdata(dev);
6517 struct drm_display_mode *vid = &it6161->source_display_mode;
6548 struct it6161 *it6161 = dev_get_drvdata(dev);
6551 for (i = 0; i < ARRAY_SIZE(it6161->sha1_input); i += 16)
6553 it6161->sha1_input + i);
6556 for (i = 0; i < ARRAY_SIZE(it6161->av); i++)
6557 str += scnprintf(str, end - str, "%4ph\n", it6161->av[i]);
6560 for (i = 0; i < ARRAY_SIZE(it6161->bv); i++)
6561 str += scnprintf(str, end - str, "%4ph\n", it6161->bv[i]);
6569 struct it6161 *it6161 = dev_get_drvdata(dev);
6571 return scnprintf(buf, PAGE_SIZE, "%d\n", it6161->enable_hdcp);
6578 struct it6161 *it6161 = dev_get_drvdata(dev);
6584 if (!it6161->powered || it6161->state == SYS_UNPLUG) {
6589 it6161->enable_hdcp = hdcp ? true : false;
6591 if (it6161->enable_hdcp) {
6592 if (it6161->cp_capable) {
6593 dptx_sys_chg(it6161, SYS_HDCP);
6594 dptx_sys_fsm(it6161);
6599 dptx_set_bits(it6161, 0x05, 0x10, 0x10);
6600 dptx_set_bits(it6161, 0x05, 0x10, 0x00);
6601 reg3f = dptx_read(it6161, 0x3F);
6613 struct it6161 *it6161 = dev_get_drvdata(dev);
6619 it6161_poweron(it6161);
6621 it6161_poweroff(it6161);
6628 struct it6161 *it6161 = dev_get_drvdata(dev);
6630 return scnprintf(buf, PAGE_SIZE, "%d\n", it6161->powered);
6651 struct it6161 *it6161 = dev_get_drvdata(&i2c_mipi_rx->dev);
6653 dptx_sys_chg(it6161, SYS_UNPLUG);
6668 static int it6161_parse_dt(struct it6161 *it6161, struct device_node *np) in it6161_parse_dt() argument
6672 it6161->host_node = of_graph_get_remote_node(np, 0, 0); in it6161_parse_dt()
6673 if (!it6161->host_node) { in it6161_parse_dt()
6678 of_node_put(it6161->host_node); in it6161_parse_dt()
6683 static int it6161_gpio_init(struct it6161 *it6161) in it6161_gpio_init() argument
6685 struct device *dev = it6161->dev; in it6161_gpio_init()
6687 it6161->enable_gpio = devm_gpiod_get_optional(dev, "enable", in it6161_gpio_init()
6689 if (IS_ERR(it6161->enable_gpio)) { in it6161_gpio_init()
6691 return PTR_ERR(it6161->enable_gpio); in it6161_gpio_init()
6694 it6161->test_gpio = devm_gpiod_get_optional(dev, "test", in it6161_gpio_init()
6696 if (IS_ERR(it6161->test_gpio)) { in it6161_gpio_init()
6701 gpiod_set_value_cansleep(it6161->enable_gpio, 1); in it6161_gpio_init()
6714 it6161 = devm_kzalloc(dev, sizeof(*it6161), GFP_KERNEL); in it6161_i2c_probe()
6715 if (!it6161) in it6161_i2c_probe()
6718 it6161_bridge = devm_kzalloc(dev, sizeof(*it6161), GFP_KERNEL); in it6161_i2c_probe()
6722 it6161->i2c_mipi_rx = i2c_mipi_rx; in it6161_i2c_probe()
6723 it6161->dev = &i2c_mipi_rx->dev; in it6161_i2c_probe()
6725 mutex_init(&it6161->mode_lock); in it6161_i2c_probe()
6727 init_completion(&it6161->wait_edid_complete); in it6161_i2c_probe()
6734 INIT_DELAYED_WORK(&it6161->restart, mipirx_restart); in it6161_i2c_probe()
6736 it6161->bridge.of_node = i2c_mipi_rx->dev.of_node; in it6161_i2c_probe()
6738 it6161_parse_dt(it6161, dev->of_node); in it6161_i2c_probe()
6739 it6161_gpio_init(it6161); in it6161_i2c_probe()
6741 it6161->regmap_mipi_rx = in it6161_i2c_probe()
6743 if (IS_ERR(it6161->regmap_mipi_rx)) { in it6161_i2c_probe()
6745 return PTR_ERR(it6161->regmap_mipi_rx); in it6161_i2c_probe()
6748 if (device_property_read_u32(dev, "it6161-addr-hdmi-tx", &it6161->it6161_addr_hdmi_tx) < 0) in it6161_i2c_probe()
6749 it6161->it6161_addr_hdmi_tx = 0x4c; in it6161_i2c_probe()
6751 it6161->i2c_hdmi_tx = i2c_new_dummy_device(i2c_mipi_rx->adapter, it6161->it6161_addr_hdmi_tx); in it6161_i2c_probe()
6752 if (IS_ERR(it6161->i2c_hdmi_tx)) { in it6161_i2c_probe()
6754 return PTR_ERR(it6161->i2c_hdmi_tx); in it6161_i2c_probe()
6757 it6161->regmap_hdmi_tx = in it6161_i2c_probe()
6758 devm_regmap_init_i2c(it6161->i2c_hdmi_tx, &it6161_hdmi_tx_bridge_regmap_config); in it6161_i2c_probe()
6760 if (IS_ERR(it6161->regmap_hdmi_tx)) { in it6161_i2c_probe()
6762 err = PTR_ERR(it6161->regmap_hdmi_tx); in it6161_i2c_probe()
6766 if (device_property_read_u32(dev, "it6161-addr-cec", &it6161->it6161_addr_cec) < 0) in it6161_i2c_probe()
6767 it6161->it6161_addr_cec = 0x4E; in it6161_i2c_probe()
6769 it6161->i2c_cec = i2c_new_dummy_device(i2c_mipi_rx->adapter, it6161->it6161_addr_cec); in it6161_i2c_probe()
6770 if (IS_ERR(it6161->i2c_cec)) { in it6161_i2c_probe()
6772 err = PTR_ERR(it6161->i2c_cec); in it6161_i2c_probe()
6776 it6161->regmap_cec = in it6161_i2c_probe()
6777 devm_regmap_init_i2c(it6161->i2c_cec, &it6161_cec_bridge_regmap_config); in it6161_i2c_probe()
6779 if (IS_ERR(it6161->regmap_cec)) { in it6161_i2c_probe()
6781 err = PTR_ERR(it6161->regmap_cec); in it6161_i2c_probe()
6785 if (!it6161_check_device_ready(it6161)) { in it6161_i2c_probe()
6790 it6161->enable_drv_hold = DEFAULT_DRV_HOLD; in it6161_i2c_probe()
6804 "it6161-intp", it6161); in it6161_i2c_probe()
6811 i2c_set_clientdata(i2c_mipi_rx, it6161); in it6161_i2c_probe()
6812 it6161->bridge.funcs = &it6161_bridge_funcs; in it6161_i2c_probe()
6813 drm_bridge_add(&it6161->bridge); in it6161_i2c_probe()
6818 i2c_unregister_device(it6161->i2c_cec); in it6161_i2c_probe()
6820 i2c_unregister_device(it6161->i2c_hdmi_tx); in it6161_i2c_probe()
6828 struct it6161 *it6161 = i2c_get_clientdata(i2c_mipi_rx);
6830 drm_connector_unregister(&it6161->connector);
6831 drm_connector_cleanup(&it6161->connector);
6832 drm_bridge_remove(&it6161->bridge);