Lines Matching refs:ast
42 struct ast_private *ast = to_ast_private(dev); in ast_enable_vga() local
44 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01); in ast_enable_vga()
45 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01); in ast_enable_vga()
50 struct ast_private *ast = to_ast_private(dev); in ast_enable_mmio() local
52 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); in ast_enable_mmio()
58 struct ast_private *ast = to_ast_private(dev); in ast_is_vga_enabled() local
61 ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT); in ast_is_vga_enabled()
73 struct ast_private *ast = to_ast_private(dev); in ast_set_def_ext_reg() local
79 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); in ast_set_def_ext_reg()
81 if (ast->chip == AST2300 || ast->chip == AST2400 || in ast_set_def_ext_reg()
82 ast->chip == AST2500) { in ast_set_def_ext_reg()
92 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info); in ast_set_def_ext_reg()
101 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01); in ast_set_def_ext_reg()
102 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00); in ast_set_def_ext_reg()
106 if (ast->chip == AST2300 || ast->chip == AST2400 || in ast_set_def_ext_reg()
107 ast->chip == AST2500) in ast_set_def_ext_reg()
109 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg); in ast_set_def_ext_reg()
112 u32 ast_mindwm(struct ast_private *ast, u32 r) in ast_mindwm() argument
116 ast_write32(ast, 0xf004, r & 0xffff0000); in ast_mindwm()
117 ast_write32(ast, 0xf000, 0x1); in ast_mindwm()
120 data = ast_read32(ast, 0xf004) & 0xffff0000; in ast_mindwm()
122 return ast_read32(ast, 0x10000 + (r & 0x0000ffff)); in ast_mindwm()
125 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v) in ast_moutdwm() argument
128 ast_write32(ast, 0xf004, r & 0xffff0000); in ast_moutdwm()
129 ast_write32(ast, 0xf000, 0x1); in ast_moutdwm()
131 data = ast_read32(ast, 0xf004) & 0xffff0000; in ast_moutdwm()
133 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v); in ast_moutdwm()
164 static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen) in mmctestburst2_ast2150() argument
168 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
169 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3)); in mmctestburst2_ast2150()
172 data = ast_mindwm(ast, 0x1e6e0070) & 0x40; in mmctestburst2_ast2150()
174 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
178 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
179 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3)); in mmctestburst2_ast2150()
182 data = ast_mindwm(ast, 0x1e6e0070) & 0x40; in mmctestburst2_ast2150()
184 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
188 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7; in mmctestburst2_ast2150()
189 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
194 static u32 mmctestsingle2_ast2150(struct ast_private *ast, u32 datagen)
198 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
199 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
202 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
204 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
208 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
209 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
214 static int cbrtest_ast2150(struct ast_private *ast) in cbrtest_ast2150() argument
219 if (mmctestburst2_ast2150(ast, i)) in cbrtest_ast2150()
224 static int cbrscan_ast2150(struct ast_private *ast, int busw) in cbrscan_ast2150() argument
229 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]); in cbrscan_ast2150()
231 if (cbrtest_ast2150(ast)) in cbrscan_ast2150()
241 static void cbrdlli_ast2150(struct ast_private *ast, int busw) in cbrdlli_ast2150() argument
251 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); in cbrdlli_ast2150()
252 data = cbrscan_ast2150(ast, busw); in cbrdlli_ast2150()
268 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); in cbrdlli_ast2150()
275 struct ast_private *ast = to_ast_private(dev); in ast_init_dram_reg() local
280 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_init_dram_reg()
283 if (ast->chip == AST2000) { in ast_init_dram_reg()
285 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_init_dram_reg()
286 ast_write32(ast, 0xf000, 0x1); in ast_init_dram_reg()
287 ast_write32(ast, 0x10100, 0xa8); in ast_init_dram_reg()
291 } while (ast_read32(ast, 0x10100) != 0xa8); in ast_init_dram_reg()
293 if (ast->chip == AST2100 || ast->chip == 2200) in ast_init_dram_reg()
298 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_init_dram_reg()
299 ast_write32(ast, 0xf000, 0x1); in ast_init_dram_reg()
300 ast_write32(ast, 0x12000, 0x1688A8A8); in ast_init_dram_reg()
303 } while (ast_read32(ast, 0x12000) != 0x01); in ast_init_dram_reg()
305 ast_write32(ast, 0x10000, 0xfc600309); in ast_init_dram_reg()
308 } while (ast_read32(ast, 0x10000) != 0x01); in ast_init_dram_reg()
315 } else if (dram_reg_info->index == 0x4 && ast->chip != AST2000) { in ast_init_dram_reg()
317 if (ast->dram_type == AST_DRAM_1Gx16) in ast_init_dram_reg()
319 else if (ast->dram_type == AST_DRAM_1Gx32) in ast_init_dram_reg()
322 temp = ast_read32(ast, 0x12070); in ast_init_dram_reg()
325 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp); in ast_init_dram_reg()
327 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data); in ast_init_dram_reg()
332 data = ast_read32(ast, 0x10120); in ast_init_dram_reg()
334 data = ast_read32(ast, 0x10004); in ast_init_dram_reg()
336 cbrdlli_ast2150(ast, 16); /* 16 bits */ in ast_init_dram_reg()
338 cbrdlli_ast2150(ast, 32); /* 32 bits */ in ast_init_dram_reg()
341 switch (ast->chip) { in ast_init_dram_reg()
343 temp = ast_read32(ast, 0x10140); in ast_init_dram_reg()
344 ast_write32(ast, 0x10140, temp | 0x40); in ast_init_dram_reg()
350 temp = ast_read32(ast, 0x1200c); in ast_init_dram_reg()
351 ast_write32(ast, 0x1200c, temp & 0xfffffffd); in ast_init_dram_reg()
352 temp = ast_read32(ast, 0x12040); in ast_init_dram_reg()
353 ast_write32(ast, 0x12040, temp | 0x40); in ast_init_dram_reg()
362 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_init_dram_reg()
368 struct ast_private *ast = to_ast_private(dev); in ast_post_gpu() local
376 ast_open_key(ast); in ast_post_gpu()
380 if (ast->config_mode == ast_use_p2a) { in ast_post_gpu()
381 if (ast->chip == AST2500) in ast_post_gpu()
383 else if (ast->chip == AST2300 || ast->chip == AST2400) in ast_post_gpu()
390 if (ast->tx_chip_type != AST_TX_NONE) in ast_post_gpu()
391 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */ in ast_post_gpu()
448 static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl) in mmc_test() argument
452 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test()
453 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); in mmc_test()
456 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000; in mmc_test()
460 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test()
464 ast_moutdwm(ast, 0x1e6e0070, 0x0); in mmc_test()
468 static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl) in mmc_test2() argument
472 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test2()
473 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); in mmc_test2()
476 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000; in mmc_test2()
478 ast_moutdwm(ast, 0x1e6e0070, 0x0); in mmc_test2()
482 data = ast_mindwm(ast, 0x1e6e0078); in mmc_test2()
484 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test2()
489 static bool mmc_test_burst(struct ast_private *ast, u32 datagen) in mmc_test_burst() argument
491 return mmc_test(ast, datagen, 0xc1); in mmc_test_burst()
494 static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen) in mmc_test_burst2() argument
496 return mmc_test2(ast, datagen, 0x41); in mmc_test_burst2()
499 static bool mmc_test_single(struct ast_private *ast, u32 datagen) in mmc_test_single() argument
501 return mmc_test(ast, datagen, 0xc5); in mmc_test_single()
504 static u32 mmc_test_single2(struct ast_private *ast, u32 datagen) in mmc_test_single2() argument
506 return mmc_test2(ast, datagen, 0x05); in mmc_test_single2()
509 static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen) in mmc_test_single_2500() argument
511 return mmc_test(ast, datagen, 0x85); in mmc_test_single_2500()
514 static int cbr_test(struct ast_private *ast) in cbr_test() argument
518 data = mmc_test_single2(ast, 0); in cbr_test()
522 data = mmc_test_burst2(ast, i); in cbr_test()
533 static int cbr_scan(struct ast_private *ast) in cbr_scan() argument
539 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); in cbr_scan()
541 if ((data = cbr_test(ast)) != 0) { in cbr_scan()
554 static u32 cbr_test2(struct ast_private *ast) in cbr_test2() argument
558 data = mmc_test_burst2(ast, 0); in cbr_test2()
561 data |= mmc_test_single2(ast, 0); in cbr_test2()
568 static u32 cbr_scan2(struct ast_private *ast) in cbr_scan2() argument
574 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); in cbr_scan2()
576 if ((data = cbr_test2(ast)) != 0) { in cbr_scan2()
589 static bool cbr_test3(struct ast_private *ast) in cbr_test3() argument
591 if (!mmc_test_burst(ast, 0)) in cbr_test3()
593 if (!mmc_test_single(ast, 0)) in cbr_test3()
598 static bool cbr_scan3(struct ast_private *ast) in cbr_scan3() argument
603 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); in cbr_scan3()
605 if (cbr_test3(ast)) in cbr_scan3()
614 static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param) in finetuneDQI_L() argument
625 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); in finetuneDQI_L()
626 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1); in finetuneDQI_L()
627 data = cbr_scan2(ast); in finetuneDQI_L()
684 ast_moutdwm(ast, 0x1E6E0080, data); in finetuneDQI_L()
709 ast_moutdwm(ast, 0x1E6E0084, data); in finetuneDQI_L()
713 static void finetuneDQSI(struct ast_private *ast) in finetuneDQSI() argument
722 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C); in finetuneDQSI()
723 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018); in finetuneDQSI()
725 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); in finetuneDQSI()
740 ast_moutdwm(ast, 0x1E6E000C, 0); in finetuneDQSI()
741 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23)); in finetuneDQSI()
742 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c); in finetuneDQSI()
744 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); in finetuneDQSI()
745 ast_moutdwm(ast, 0x1E6E0070, 0); in finetuneDQSI()
746 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0); in finetuneDQSI()
747 if (cbr_scan3(ast)) { in finetuneDQSI()
800 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); in finetuneDQSI()
803 static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param) in cbr_dll2() argument
808 finetuneDQSI(ast); in cbr_dll2()
809 if (finetuneDQI_L(ast, param) == false) in cbr_dll2()
817 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); in cbr_dll2()
818 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2); in cbr_dll2()
819 data = cbr_scan(ast); in cbr_dll2()
855 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16)); in cbr_dll2()
859 static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param) in get_ddr3_info() argument
863 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); in get_ddr3_info()
866 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; in get_ddr3_info()
880 ast_moutdwm(ast, 0x1E6E2020, 0x0190); in get_ddr3_info()
908 ast_moutdwm(ast, 0x1E6E2020, 0x03F1); in get_ddr3_info()
938 ast_moutdwm(ast, 0x1E6E2020, 0x01F0); in get_ddr3_info()
968 ast_moutdwm(ast, 0x1E6E2020, 0x0230); in get_ddr3_info()
982 ast_moutdwm(ast, 0x1E6E2020, 0x0270); in get_ddr3_info()
996 ast_moutdwm(ast, 0x1E6E2020, 0x0290); in get_ddr3_info()
1012 ast_moutdwm(ast, 0x1E6E2020, 0x0140); in get_ddr3_info()
1030 ast_moutdwm(ast, 0x1E6E2020, 0x02E1); in get_ddr3_info()
1048 ast_moutdwm(ast, 0x1E6E2020, 0x0160); in get_ddr3_info()
1101 static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param) in ddr3_init() argument
1106 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in ddr3_init()
1107 ast_moutdwm(ast, 0x1E6E0018, 0x00000100); in ddr3_init()
1108 ast_moutdwm(ast, 0x1E6E0024, 0x00000000); in ddr3_init()
1109 ast_moutdwm(ast, 0x1E6E0034, 0x00000000); in ddr3_init()
1111 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); in ddr3_init()
1112 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); in ddr3_init()
1114 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); in ddr3_init()
1117 ast_moutdwm(ast, 0x1E6E0004, param->dram_config); in ddr3_init()
1118 ast_moutdwm(ast, 0x1E6E0008, 0x90040f); in ddr3_init()
1119 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); in ddr3_init()
1120 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); in ddr3_init()
1121 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); in ddr3_init()
1122 ast_moutdwm(ast, 0x1E6E0080, 0x00000000); in ddr3_init()
1123 ast_moutdwm(ast, 0x1E6E0084, 0x00000000); in ddr3_init()
1124 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); in ddr3_init()
1125 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170); in ddr3_init()
1126 ast_moutdwm(ast, 0x1E6E0018, 0x00002370); in ddr3_init()
1127 ast_moutdwm(ast, 0x1E6E0038, 0x00000000); in ddr3_init()
1128 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444); in ddr3_init()
1129 ast_moutdwm(ast, 0x1E6E0044, 0x22222222); in ddr3_init()
1130 ast_moutdwm(ast, 0x1E6E0048, 0x22222222); in ddr3_init()
1131 ast_moutdwm(ast, 0x1E6E004C, 0x00000002); in ddr3_init()
1132 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr3_init()
1133 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr3_init()
1134 ast_moutdwm(ast, 0x1E6E0054, 0); in ddr3_init()
1135 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); in ddr3_init()
1136 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); in ddr3_init()
1137 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr3_init()
1138 ast_moutdwm(ast, 0x1E6E0074, 0x00000000); in ddr3_init()
1139 ast_moutdwm(ast, 0x1E6E0078, 0x00000000); in ddr3_init()
1140 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr3_init()
1143 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1145 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1148 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; in ddr3_init()
1152 ast_moutdwm(ast, 0x1E6E0064, data2); in ddr3_init()
1158 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; in ddr3_init()
1161 ast_moutdwm(ast, 0x1E6E0068, data); in ddr3_init()
1163 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); in ddr3_init()
1165 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; in ddr3_init()
1166 ast_moutdwm(ast, 0x1E6E0018, data); in ddr3_init()
1168 ast_moutdwm(ast, 0x1E6E0018, data); in ddr3_init()
1170 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1173 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1176 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff); in ddr3_init()
1177 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; in ddr3_init()
1178 ast_moutdwm(ast, 0x1E6E0018, data); in ddr3_init()
1180 ast_moutdwm(ast, 0x1E6E0034, 0x00000001); in ddr3_init()
1181 ast_moutdwm(ast, 0x1E6E000C, 0x00000040); in ddr3_init()
1184 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); in ddr3_init()
1185 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); in ddr3_init()
1186 ast_moutdwm(ast, 0x1E6E0028, 0x00000005); in ddr3_init()
1187 ast_moutdwm(ast, 0x1E6E0028, 0x00000007); in ddr3_init()
1188 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr3_init()
1189 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr3_init()
1190 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); in ddr3_init()
1191 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); in ddr3_init()
1192 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr3_init()
1194 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); in ddr3_init()
1202 ast_moutdwm(ast, 0x1E6E0034, data | 0x3); in ddr3_init()
1205 if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) in ddr3_init()
1208 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); in ddr3_init()
1211 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr3_init()
1212 ast_moutdwm(ast, 0x1E6E0070, 0x221); in ddr3_init()
1214 data = ast_mindwm(ast, 0x1E6E0070); in ddr3_init()
1216 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr3_init()
1217 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr3_init()
1218 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr3_init()
1224 static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param) in get_ddr2_info() argument
1228 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); in get_ddr2_info()
1231 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; in get_ddr2_info()
1245 ast_moutdwm(ast, 0x1E6E2020, 0x0130); in get_ddr2_info()
1260 ast_moutdwm(ast, 0x1E6E2020, 0x0190); in get_ddr2_info()
1291 ast_moutdwm(ast, 0x1E6E2020, 0x03F1); in get_ddr2_info()
1325 ast_moutdwm(ast, 0x1E6E2020, 0x01F0); in get_ddr2_info()
1358 ast_moutdwm(ast, 0x1E6E2020, 0x0230); in get_ddr2_info()
1373 ast_moutdwm(ast, 0x1E6E2020, 0x0261); in get_ddr2_info()
1389 ast_moutdwm(ast, 0x1E6E2020, 0x0120); in get_ddr2_info()
1405 ast_moutdwm(ast, 0x1E6E2020, 0x02A1); in get_ddr2_info()
1421 ast_moutdwm(ast, 0x1E6E2020, 0x0140); in get_ddr2_info()
1471 static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param) in ddr2_init() argument
1476 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in ddr2_init()
1477 ast_moutdwm(ast, 0x1E6E0018, 0x00000100); in ddr2_init()
1478 ast_moutdwm(ast, 0x1E6E0024, 0x00000000); in ddr2_init()
1479 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); in ddr2_init()
1480 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); in ddr2_init()
1482 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); in ddr2_init()
1485 ast_moutdwm(ast, 0x1E6E0004, param->dram_config); in ddr2_init()
1486 ast_moutdwm(ast, 0x1E6E0008, 0x90040f); in ddr2_init()
1487 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); in ddr2_init()
1488 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); in ddr2_init()
1489 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); in ddr2_init()
1490 ast_moutdwm(ast, 0x1E6E0080, 0x00000000); in ddr2_init()
1491 ast_moutdwm(ast, 0x1E6E0084, 0x00000000); in ddr2_init()
1492 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); in ddr2_init()
1493 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130); in ddr2_init()
1494 ast_moutdwm(ast, 0x1E6E0018, 0x00002330); in ddr2_init()
1495 ast_moutdwm(ast, 0x1E6E0038, 0x00000000); in ddr2_init()
1496 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000); in ddr2_init()
1497 ast_moutdwm(ast, 0x1E6E0044, 0x88848466); in ddr2_init()
1498 ast_moutdwm(ast, 0x1E6E0048, 0x44440008); in ddr2_init()
1499 ast_moutdwm(ast, 0x1E6E004C, 0x00000000); in ddr2_init()
1500 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr2_init()
1501 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr2_init()
1502 ast_moutdwm(ast, 0x1E6E0054, 0); in ddr2_init()
1503 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); in ddr2_init()
1504 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); in ddr2_init()
1505 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr2_init()
1506 ast_moutdwm(ast, 0x1E6E0074, 0x00000000); in ddr2_init()
1507 ast_moutdwm(ast, 0x1E6E0078, 0x00000000); in ddr2_init()
1508 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr2_init()
1512 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1514 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1517 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; in ddr2_init()
1521 ast_moutdwm(ast, 0x1E6E0064, data2); in ddr2_init()
1527 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; in ddr2_init()
1530 ast_moutdwm(ast, 0x1E6E0068, data); in ddr2_init()
1532 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); in ddr2_init()
1534 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; in ddr2_init()
1535 ast_moutdwm(ast, 0x1E6E0018, data); in ddr2_init()
1537 ast_moutdwm(ast, 0x1E6E0018, data); in ddr2_init()
1539 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1542 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1545 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff); in ddr2_init()
1546 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; in ddr2_init()
1547 ast_moutdwm(ast, 0x1E6E0018, data); in ddr2_init()
1549 ast_moutdwm(ast, 0x1E6E0034, 0x00000001); in ddr2_init()
1550 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr2_init()
1553 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); in ddr2_init()
1554 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); in ddr2_init()
1555 ast_moutdwm(ast, 0x1E6E0028, 0x00000005); in ddr2_init()
1556 ast_moutdwm(ast, 0x1E6E0028, 0x00000007); in ddr2_init()
1557 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr2_init()
1558 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr2_init()
1560 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); in ddr2_init()
1561 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); in ddr2_init()
1562 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr2_init()
1563 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380); in ddr2_init()
1564 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr2_init()
1565 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); in ddr2_init()
1566 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr2_init()
1568 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01); in ddr2_init()
1576 ast_moutdwm(ast, 0x1E6E0034, data | 0x3); in ddr2_init()
1577 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); in ddr2_init()
1580 if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) in ddr2_init()
1585 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr2_init()
1586 ast_moutdwm(ast, 0x1E6E0070, 0x221); in ddr2_init()
1588 data = ast_mindwm(ast, 0x1E6E0070); in ddr2_init()
1590 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr2_init()
1591 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr2_init()
1592 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr2_init()
1599 struct ast_private *ast = to_ast_private(dev); in ast_post_chip_2300() local
1604 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_post_chip_2300()
1606 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_post_chip_2300()
1607 ast_write32(ast, 0xf000, 0x1); in ast_post_chip_2300()
1608 ast_write32(ast, 0x12000, 0x1688a8a8); in ast_post_chip_2300()
1611 } while (ast_read32(ast, 0x12000) != 0x1); in ast_post_chip_2300()
1613 ast_write32(ast, 0x10000, 0xfc600309); in ast_post_chip_2300()
1616 } while (ast_read32(ast, 0x10000) != 0x1); in ast_post_chip_2300()
1619 temp = ast_read32(ast, 0x12008); in ast_post_chip_2300()
1621 ast_write32(ast, 0x12008, temp); in ast_post_chip_2300()
1625 temp = ast_mindwm(ast, 0x1e6e2070); in ast_post_chip_2300()
1663 get_ddr3_info(ast, ¶m); in ast_post_chip_2300()
1664 ddr3_init(ast, ¶m); in ast_post_chip_2300()
1666 get_ddr2_info(ast, ¶m); in ast_post_chip_2300()
1667 ddr2_init(ast, ¶m); in ast_post_chip_2300()
1670 temp = ast_mindwm(ast, 0x1e6e2040); in ast_post_chip_2300()
1671 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); in ast_post_chip_2300()
1676 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_post_chip_2300()
1680 static bool cbr_test_2500(struct ast_private *ast) in cbr_test_2500() argument
1682 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); in cbr_test_2500()
1683 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); in cbr_test_2500()
1684 if (!mmc_test_burst(ast, 0)) in cbr_test_2500()
1686 if (!mmc_test_single_2500(ast, 0)) in cbr_test_2500()
1691 static bool ddr_test_2500(struct ast_private *ast) in ddr_test_2500() argument
1693 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); in ddr_test_2500()
1694 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); in ddr_test_2500()
1695 if (!mmc_test_burst(ast, 0)) in ddr_test_2500()
1697 if (!mmc_test_burst(ast, 1)) in ddr_test_2500()
1699 if (!mmc_test_burst(ast, 2)) in ddr_test_2500()
1701 if (!mmc_test_burst(ast, 3)) in ddr_test_2500()
1703 if (!mmc_test_single_2500(ast, 0)) in ddr_test_2500()
1708 static void ddr_init_common_2500(struct ast_private *ast) in ddr_init_common_2500() argument
1710 ast_moutdwm(ast, 0x1E6E0034, 0x00020080); in ddr_init_common_2500()
1711 ast_moutdwm(ast, 0x1E6E0008, 0x2003000F); in ddr_init_common_2500()
1712 ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF); in ddr_init_common_2500()
1713 ast_moutdwm(ast, 0x1E6E0040, 0x88448844); in ddr_init_common_2500()
1714 ast_moutdwm(ast, 0x1E6E0044, 0x24422288); in ddr_init_common_2500()
1715 ast_moutdwm(ast, 0x1E6E0048, 0x22222222); in ddr_init_common_2500()
1716 ast_moutdwm(ast, 0x1E6E004C, 0x22222222); in ddr_init_common_2500()
1717 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr_init_common_2500()
1718 ast_moutdwm(ast, 0x1E6E0208, 0x00000000); in ddr_init_common_2500()
1719 ast_moutdwm(ast, 0x1E6E0218, 0x00000000); in ddr_init_common_2500()
1720 ast_moutdwm(ast, 0x1E6E0220, 0x00000000); in ddr_init_common_2500()
1721 ast_moutdwm(ast, 0x1E6E0228, 0x00000000); in ddr_init_common_2500()
1722 ast_moutdwm(ast, 0x1E6E0230, 0x00000000); in ddr_init_common_2500()
1723 ast_moutdwm(ast, 0x1E6E02A8, 0x00000000); in ddr_init_common_2500()
1724 ast_moutdwm(ast, 0x1E6E02B0, 0x00000000); in ddr_init_common_2500()
1725 ast_moutdwm(ast, 0x1E6E0240, 0x86000000); in ddr_init_common_2500()
1726 ast_moutdwm(ast, 0x1E6E0244, 0x00008600); in ddr_init_common_2500()
1727 ast_moutdwm(ast, 0x1E6E0248, 0x80000000); in ddr_init_common_2500()
1728 ast_moutdwm(ast, 0x1E6E024C, 0x80808080); in ddr_init_common_2500()
1731 static void ddr_phy_init_2500(struct ast_private *ast) in ddr_phy_init_2500() argument
1736 ast_moutdwm(ast, 0x1E6E0060, 0x00000005); in ddr_phy_init_2500()
1739 data = ast_mindwm(ast, 0x1E6E0060) & 0x1; in ddr_phy_init_2500()
1744 data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000; in ddr_phy_init_2500()
1749 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr_phy_init_2500()
1751 ast_moutdwm(ast, 0x1E6E0060, 0x00000005); in ddr_phy_init_2500()
1755 ast_moutdwm(ast, 0x1E6E0060, 0x00000006); in ddr_phy_init_2500()
1765 static void check_dram_size_2500(struct ast_private *ast, u32 tRFC) in check_dram_size_2500() argument
1769 reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc; in check_dram_size_2500()
1770 reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00; in check_dram_size_2500()
1772 ast_moutdwm(ast, 0xA0100000, 0x41424344); in check_dram_size_2500()
1773 ast_moutdwm(ast, 0x90100000, 0x35363738); in check_dram_size_2500()
1774 ast_moutdwm(ast, 0x88100000, 0x292A2B2C); in check_dram_size_2500()
1775 ast_moutdwm(ast, 0x80100000, 0x1D1E1F10); in check_dram_size_2500()
1778 if (ast_mindwm(ast, 0xA0100000) == 0x41424344) { in check_dram_size_2500()
1782 } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) { in check_dram_size_2500()
1786 } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) { in check_dram_size_2500()
1792 ast_moutdwm(ast, 0x1E6E0004, reg_04); in check_dram_size_2500()
1793 ast_moutdwm(ast, 0x1E6E0014, reg_14); in check_dram_size_2500()
1796 static void enable_cache_2500(struct ast_private *ast) in enable_cache_2500() argument
1800 reg_04 = ast_mindwm(ast, 0x1E6E0004); in enable_cache_2500()
1801 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000); in enable_cache_2500()
1804 data = ast_mindwm(ast, 0x1E6E0004); in enable_cache_2500()
1806 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400); in enable_cache_2500()
1809 static void set_mpll_2500(struct ast_private *ast) in set_mpll_2500() argument
1814 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in set_mpll_2500()
1815 ast_moutdwm(ast, 0x1E6E0034, 0x00020080); in set_mpll_2500()
1817 ast_moutdwm(ast, addr, 0x0); in set_mpll_2500()
1820 ast_moutdwm(ast, 0x1E6E0034, 0x00020000); in set_mpll_2500()
1822 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); in set_mpll_2500()
1823 data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000; in set_mpll_2500()
1827 ast_moutdwm(ast, 0x1E6E2160, 0x00011320); in set_mpll_2500()
1832 ast_moutdwm(ast, 0x1E6E2020, param); in set_mpll_2500()
1836 static void reset_mmc_2500(struct ast_private *ast) in reset_mmc_2500() argument
1838 ast_moutdwm(ast, 0x1E78505C, 0x00000004); in reset_mmc_2500()
1839 ast_moutdwm(ast, 0x1E785044, 0x00000001); in reset_mmc_2500()
1840 ast_moutdwm(ast, 0x1E785048, 0x00004755); in reset_mmc_2500()
1841 ast_moutdwm(ast, 0x1E78504C, 0x00000013); in reset_mmc_2500()
1843 ast_moutdwm(ast, 0x1E785054, 0x00000077); in reset_mmc_2500()
1844 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in reset_mmc_2500()
1847 static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table) in ddr3_init_2500() argument
1850 ast_moutdwm(ast, 0x1E6E0004, 0x00000303); in ddr3_init_2500()
1851 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); in ddr3_init_2500()
1852 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); in ddr3_init_2500()
1853 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); in ddr3_init_2500()
1854 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ in ddr3_init_2500()
1855 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ in ddr3_init_2500()
1856 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ in ddr3_init_2500()
1857 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ in ddr3_init_2500()
1860 ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE); in ddr3_init_2500()
1861 ast_moutdwm(ast, 0x1E6E0204, 0x00001001); in ddr3_init_2500()
1862 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); in ddr3_init_2500()
1863 ast_moutdwm(ast, 0x1E6E0210, 0x20000000); in ddr3_init_2500()
1864 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); in ddr3_init_2500()
1865 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); in ddr3_init_2500()
1866 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); in ddr3_init_2500()
1867 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); in ddr3_init_2500()
1868 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); in ddr3_init_2500()
1869 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); in ddr3_init_2500()
1870 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); in ddr3_init_2500()
1871 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); in ddr3_init_2500()
1872 ast_moutdwm(ast, 0x1E6E0290, 0x00100008); in ddr3_init_2500()
1873 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006); in ddr3_init_2500()
1876 ast_moutdwm(ast, 0x1E6E0034, 0x00020091); in ddr3_init_2500()
1879 ddr_phy_init_2500(ast); in ddr3_init_2500()
1881 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); in ddr3_init_2500()
1882 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); in ddr3_init_2500()
1883 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); in ddr3_init_2500()
1885 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); in ddr3_init_2500()
1886 enable_cache_2500(ast); in ddr3_init_2500()
1887 ast_moutdwm(ast, 0x1E6E001C, 0x00000008); in ddr3_init_2500()
1888 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); in ddr3_init_2500()
1891 static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table) in ddr4_init_2500() argument
1898 ast_moutdwm(ast, 0x1E6E0004, 0x00000313); in ddr4_init_2500()
1899 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); in ddr4_init_2500()
1900 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); in ddr4_init_2500()
1901 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); in ddr4_init_2500()
1902 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ in ddr4_init_2500()
1903 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ in ddr4_init_2500()
1904 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ in ddr4_init_2500()
1905 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ in ddr4_init_2500()
1908 ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE); in ddr4_init_2500()
1909 ast_moutdwm(ast, 0x1E6E0204, 0x09002000); in ddr4_init_2500()
1910 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); in ddr4_init_2500()
1911 ast_moutdwm(ast, 0x1E6E0210, 0x20000000); in ddr4_init_2500()
1912 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); in ddr4_init_2500()
1913 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); in ddr4_init_2500()
1914 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); in ddr4_init_2500()
1915 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); in ddr4_init_2500()
1916 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); in ddr4_init_2500()
1917 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); in ddr4_init_2500()
1918 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); in ddr4_init_2500()
1919 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); in ddr4_init_2500()
1920 ast_moutdwm(ast, 0x1E6E0290, 0x00100008); in ddr4_init_2500()
1921 ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C); in ddr4_init_2500()
1922 ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E); in ddr4_init_2500()
1925 ast_moutdwm(ast, 0x1E6E0034, 0x0001A991); in ddr4_init_2500()
1933 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06); in ddr4_init_2500()
1935 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr4_init_2500()
1936 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr4_init_2500()
1937 ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8)); in ddr4_init_2500()
1939 ddr_phy_init_2500(ast); in ddr4_init_2500()
1940 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); in ddr4_init_2500()
1941 if (cbr_test_2500(ast)) { in ddr4_init_2500()
1943 data = ast_mindwm(ast, 0x1E6E03D0); in ddr4_init_2500()
1956 ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8)); in ddr4_init_2500()
1966 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr4_init_2500()
1967 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr4_init_2500()
1968 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); in ddr4_init_2500()
1970 ddr_phy_init_2500(ast); in ddr4_init_2500()
1971 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); in ddr4_init_2500()
1972 if (cbr_test_2500(ast)) { in ddr4_init_2500()
1983 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr4_init_2500()
1984 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr4_init_2500()
1986 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); in ddr4_init_2500()
1989 ddr_phy_init_2500(ast); in ddr4_init_2500()
1991 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); in ddr4_init_2500()
1992 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); in ddr4_init_2500()
1993 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); in ddr4_init_2500()
1995 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); in ddr4_init_2500()
1996 enable_cache_2500(ast); in ddr4_init_2500()
1997 ast_moutdwm(ast, 0x1E6E001C, 0x00000008); in ddr4_init_2500()
1998 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); in ddr4_init_2500()
2001 static bool ast_dram_init_2500(struct ast_private *ast) in ast_dram_init_2500() argument
2009 set_mpll_2500(ast); in ast_dram_init_2500()
2010 reset_mmc_2500(ast); in ast_dram_init_2500()
2011 ddr_init_common_2500(ast); in ast_dram_init_2500()
2013 data = ast_mindwm(ast, 0x1E6E2070); in ast_dram_init_2500()
2015 ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table); in ast_dram_init_2500()
2017 ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table); in ast_dram_init_2500()
2018 } while (!ddr_test_2500(ast)); in ast_dram_init_2500()
2020 ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41); in ast_dram_init_2500()
2023 data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF; in ast_dram_init_2500()
2024 ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000); in ast_dram_init_2500()
2031 struct ast_private *ast = to_ast_private(dev); in ast_post_chip_2500() local
2035 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_post_chip_2500()
2038 ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); in ast_post_chip_2500()
2039 ast_moutdwm(ast, 0x1e600084, 0x00010000); in ast_post_chip_2500()
2040 ast_moutdwm(ast, 0x1e600088, 0x00000000); in ast_post_chip_2500()
2041 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); in ast_post_chip_2500()
2042 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_post_chip_2500()
2043 ast_write32(ast, 0xf000, 0x1); in ast_post_chip_2500()
2044 ast_write32(ast, 0x12000, 0x1688a8a8); in ast_post_chip_2500()
2045 while (ast_read32(ast, 0x12000) != 0x1) in ast_post_chip_2500()
2048 ast_write32(ast, 0x10000, 0xfc600309); in ast_post_chip_2500()
2049 while (ast_read32(ast, 0x10000) != 0x1) in ast_post_chip_2500()
2053 temp = ast_read32(ast, 0x12008); in ast_post_chip_2500()
2055 ast_write32(ast, 0x12008, temp); in ast_post_chip_2500()
2058 ast_moutdwm(ast, 0x1e6e2090, 0x20000000); in ast_post_chip_2500()
2059 temp = ast_mindwm(ast, 0x1e6e2094); in ast_post_chip_2500()
2061 ast_moutdwm(ast, 0x1e6e2094, temp); in ast_post_chip_2500()
2062 temp = ast_mindwm(ast, 0x1e6e2070); in ast_post_chip_2500()
2064 ast_moutdwm(ast, 0x1e6e207c, 0x00800000); in ast_post_chip_2500()
2066 ast_moutdwm(ast, 0x1e6e2070, 0x00800000); in ast_post_chip_2500()
2069 if (!ast_dram_init_2500(ast)) in ast_post_chip_2500()
2072 temp = ast_mindwm(ast, 0x1e6e2040); in ast_post_chip_2500()
2073 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); in ast_post_chip_2500()
2078 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_post_chip_2500()