76 	*scu_rev = 0xffffffff;  in ast_detect_config_mode()
92 	 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge  in ast_detect_config_mode()
96 	jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);  in ast_detect_config_mode()
97 	jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);  in ast_detect_config_mode()
98 	if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {  in ast_detect_config_mode()
100 		data = ast_read32(ast, 0xf004);  in ast_detect_config_mode()
101 		if ((data != 0xFFFFFFFF) && (data != 0x00)) {  in ast_detect_config_mode()
108 			ast_write32(ast, 0xf004, 0x1e6e0000);  in ast_detect_config_mode()
109 			ast_write32(ast, 0xf000, 0x1);  in ast_detect_config_mode()
110 			*scu_rev = ast_read32(ast, 0x1207c);  in ast_detect_config_mode()
146 	if (dev->pdev->revision >= 0x40) {  in ast_detect_chip()
149 	} else if (dev->pdev->revision >= 0x30) {  in ast_detect_chip()
152 	} else if (dev->pdev->revision >= 0x20) {  in ast_detect_chip()
155 	} else if (dev->pdev->revision >= 0x10) {  in ast_detect_chip()
156 		switch (scu_rev & 0x0300) {  in ast_detect_chip()
157 		case 0x0200:  in ast_detect_chip()
161 		case 0x0100:  in ast_detect_chip()
165 		case 0x0000:  in ast_detect_chip()
186 		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);  in ast_detect_chip()
187 		if (!(jreg & 0x80))  in ast_detect_chip()
189 		else if (jreg & 0x01)  in ast_detect_chip()
194 			    (scu_rev & 0x300) == 0x0) /* ast1300 */  in ast_detect_chip()
197 			    (scu_rev & 0x300) == 0x100) /* ast1400 */  in ast_detect_chip()
200 			    scu_rev == 0x100)           /* ast2510 */  in ast_detect_chip()
218 		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);  in ast_detect_chip()
219 		if (jreg & 0x80)  in ast_detect_chip()
229 		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);  in ast_detect_chip()
231 		case 0x04:  in ast_detect_chip()
234 		case 0x08:  in ast_detect_chip()
244 		case 0x0c:  in ast_detect_chip()
260 	return 0;  in ast_detect_chip()
278 			mcr_cfg = 0x00000577;  in ast_get_dram_info()
281 			mcr_scu_mpll = 0x000050C0;  in ast_get_dram_info()
284 			mcr_scu_strap = 0;  in ast_get_dram_info()
287 		ast_write32(ast, 0xf004, 0x1e6e0000);  in ast_get_dram_info()
288 		ast_write32(ast, 0xf000, 0x1);  in ast_get_dram_info()
289 		mcr_cfg = ast_read32(ast, 0x10004);  in ast_get_dram_info()
290 		mcr_scu_mpll = ast_read32(ast, 0x10120);  in ast_get_dram_info()
291 		mcr_scu_strap = ast_read32(ast, 0x10170);  in ast_get_dram_info()
301 		return 0;  in ast_get_dram_info()
304 	if (mcr_cfg & 0x40)  in ast_get_dram_info()
310 		switch (mcr_cfg & 0x03) {  in ast_get_dram_info()
311 		case 0:  in ast_get_dram_info()
326 		switch (mcr_cfg & 0x03) {  in ast_get_dram_info()
327 		case 0:  in ast_get_dram_info()
342 		switch (mcr_cfg & 0x0c) {  in ast_get_dram_info()
343 		case 0:  in ast_get_dram_info()
348 			if (mcr_cfg & 0x40)  in ast_get_dram_info()
353 		case 0xc:  in ast_get_dram_info()
359 	if (mcr_scu_strap & 0x2000)  in ast_get_dram_info()
364 	denum = mcr_scu_mpll & 0x1f;  in ast_get_dram_info()
365 	num = (mcr_scu_mpll & 0x3fe0) >> 5;  in ast_get_dram_info()
366 	dsel = (mcr_scu_mpll & 0xc000) >> 14;  in ast_get_dram_info()
369 		div = 0x4;  in ast_get_dram_info()
373 		div = 0x2;  in ast_get_dram_info()
376 		div = 0x1;  in ast_get_dram_info()
380 	return 0;  in ast_get_dram_info()
392 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04);  in ast_device_release()
402 	int ret = 0;  in ast_device_create()
412 	ast->regs = pcim_iomap(pdev, 1, 0);  in ast_device_create()
418 	 * assume the chip has MMIO enabled by default (rev 0x20  in ast_device_create()
428 		ast->ioregs = pcim_iomap(pdev, 2, 0);  in ast_device_create()
451 	if (dev->vram_mm->vram_size < pci_resource_len(dev->pdev, 0)) {  in ast_device_create()
452 		ast->dp501_fw_buf = pci_iomap_range(dev->pdev, 0, dev->vram_mm->vram_size, 0);  in ast_device_create()