105 	address = adev->nbio.funcs->get_pcie_index_offset(adev);  in soc15_pcie_rreg()
106 	data = adev->nbio.funcs->get_pcie_data_offset(adev);  in soc15_pcie_rreg()
115 	address = adev->nbio.funcs->get_pcie_index_offset(adev);  in soc15_pcie_wreg()
116 	data = adev->nbio.funcs->get_pcie_data_offset(adev);  in soc15_pcie_wreg()
124 	address = adev->nbio.funcs->get_pcie_index_offset(adev);  in soc15_pcie_rreg64()
125 	data = adev->nbio.funcs->get_pcie_data_offset(adev);  in soc15_pcie_rreg64()
134 	address = adev->nbio.funcs->get_pcie_index_offset(adev);  in soc15_pcie_wreg64()
135 	data = adev->nbio.funcs->get_pcie_data_offset(adev);  in soc15_pcie_wreg64()
242 	return adev->nbio.funcs->get_memsize(adev);  in soc15_get_config_memsize()
464 		u32 memsize = adev->nbio.funcs->get_memsize(adev);  in soc15_asic_mode1_reset()
483 		adev->nbio.funcs->enable_doorbell_interrupt(adev, false);  in soc15_asic_baco_reset()
491 		adev->nbio.funcs->enable_doorbell_interrupt(adev, true);  in soc15_asic_baco_reset()
633 	adev->nbio.funcs->enable_doorbell_aperture(adev, enable);  in soc15_enable_doorbell_aperture()
634 	adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);  in soc15_enable_doorbell_aperture()
648 	return adev->nbio.funcs->get_rev_id(adev);  in soc15_get_rev_id()
706 		adev->nbio.funcs = &nbio_v7_0_funcs;  in soc15_set_ip_blocks()
707 		adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;  in soc15_set_ip_blocks()
710 		adev->nbio.funcs = &nbio_v7_4_funcs;  in soc15_set_ip_blocks()
711 		adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;  in soc15_set_ip_blocks()
713 		adev->nbio.funcs = &nbio_v6_1_funcs;  in soc15_set_ip_blocks()
714 		adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;  in soc15_set_ip_blocks()
841 	adev->nbio.funcs->hdp_flush(adev, ring);  in soc15_flush_hdp()
1308 	if (adev->nbio.funcs->ras_late_init)  in soc15_common_late_init()
1309 		r = adev->nbio.funcs->ras_late_init(adev);  in soc15_common_late_init()
1344 			adev->nbio.funcs->sdma_doorbell_range(adev, i,  in soc15_doorbell_range_init()
1349 		adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,  in soc15_doorbell_range_init()
1363 	adev->nbio.funcs->init_registers(adev);  in soc15_common_hw_init()
1368 	if (adev->nbio.funcs->remap_hdp_registers)  in soc15_common_hw_init()
1369 		adev->nbio.funcs->remap_hdp_registers(adev);  in soc15_common_hw_init()
1392 	if (adev->nbio.ras_if &&  in soc15_common_hw_fini()
1393 	    amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {  in soc15_common_hw_fini()
1394 		if (adev->nbio.funcs->init_ras_controller_interrupt)  in soc15_common_hw_fini()
1395 			amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);  in soc15_common_hw_fini()
1396 		if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)  in soc15_common_hw_fini()
1397 			amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);  in soc15_common_hw_fini()
1541 		adev->nbio.funcs->update_medium_grain_clock_gating(adev,  in soc15_common_set_clockgating_state()
1543 		adev->nbio.funcs->update_medium_grain_light_sleep(adev,  in soc15_common_set_clockgating_state()
1558 		adev->nbio.funcs->update_medium_grain_clock_gating(adev,  in soc15_common_set_clockgating_state()
1560 		adev->nbio.funcs->update_medium_grain_light_sleep(adev,  in soc15_common_set_clockgating_state()
1589 	adev->nbio.funcs->get_clockgating_state(adev, flags);  in soc15_common_get_clockgating_state()