Lines Matching refs:adev
102 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) in soc15_pcie_rreg() argument
105 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg()
106 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_rreg()
108 return amdgpu_device_indirect_rreg(adev, address, data, reg); in soc15_pcie_rreg()
111 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_pcie_wreg() argument
115 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_wreg()
116 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_wreg()
118 amdgpu_device_indirect_wreg(adev, address, data, reg, v); in soc15_pcie_wreg()
121 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) in soc15_pcie_rreg64() argument
124 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg64()
125 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_rreg64()
127 return amdgpu_device_indirect_rreg64(adev, address, data, reg); in soc15_pcie_rreg64()
130 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) in soc15_pcie_wreg64() argument
134 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_wreg64()
135 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_wreg64()
137 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); in soc15_pcie_wreg64()
140 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) in soc15_uvd_ctx_rreg() argument
148 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
151 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
155 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_uvd_ctx_wreg() argument
162 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
165 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
168 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) in soc15_didt_rreg() argument
176 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
179 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
183 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_didt_wreg() argument
190 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
193 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
196 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) in soc15_gc_cac_rreg() argument
201 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
204 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
208 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_gc_cac_wreg() argument
212 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
215 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
218 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) in soc15_se_cac_rreg() argument
223 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
226 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
230 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_se_cac_wreg() argument
234 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
237 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
240 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) in soc15_get_config_memsize() argument
242 return adev->nbio.funcs->get_memsize(adev); in soc15_get_config_memsize()
245 static u32 soc15_get_xclk(struct amdgpu_device *adev) in soc15_get_xclk() argument
247 u32 reference_clock = adev->clock.spll.reference_freq; in soc15_get_xclk()
249 if (adev->asic_type == CHIP_RENOIR) in soc15_get_xclk()
251 if (adev->asic_type == CHIP_RAVEN) in soc15_get_xclk()
258 void soc15_grbm_select(struct amdgpu_device *adev, in soc15_grbm_select() argument
270 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) in soc15_vga_set_state() argument
275 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) in soc15_read_disabled_bios() argument
281 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, in soc15_read_bios_from_rom() argument
294 if (adev->flags & AMD_IS_APU) in soc15_read_bios_from_rom()
300 switch (adev->asic_type) { in soc15_read_bios_from_rom()
344 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_indexed_register() argument
349 mutex_lock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
351 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in soc15_read_indexed_register()
356 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in soc15_read_indexed_register()
357 mutex_unlock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
361 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, in soc15_get_register_value() argument
366 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
369 return adev->gfx.config.gb_addr_config; in soc15_get_register_value()
371 return adev->gfx.config.db_debug2; in soc15_get_register_value()
376 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_register() argument
385 if (adev->reg_offset[en->hwip][en->inst] && in soc15_read_register()
386 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc15_read_register()
390 *value = soc15_get_register_value(adev, in soc15_read_register()
410 void soc15_program_register_sequence(struct amdgpu_device *adev, in soc15_program_register_sequence() argument
420 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in soc15_program_register_sequence()
442 static int soc15_asic_mode1_reset(struct amdgpu_device *adev) in soc15_asic_mode1_reset() argument
447 amdgpu_atombios_scratch_regs_engine_hung(adev, true); in soc15_asic_mode1_reset()
449 dev_info(adev->dev, "GPU mode1 reset\n"); in soc15_asic_mode1_reset()
452 pci_clear_master(adev->pdev); in soc15_asic_mode1_reset()
454 amdgpu_device_cache_pci_state(adev->pdev); in soc15_asic_mode1_reset()
456 ret = psp_gpu_reset(adev); in soc15_asic_mode1_reset()
458 dev_err(adev->dev, "GPU mode1 reset failed\n"); in soc15_asic_mode1_reset()
460 amdgpu_device_load_pci_state(adev->pdev); in soc15_asic_mode1_reset()
463 for (i = 0; i < adev->usec_timeout; i++) { in soc15_asic_mode1_reset()
464 u32 memsize = adev->nbio.funcs->get_memsize(adev); in soc15_asic_mode1_reset()
471 amdgpu_atombios_scratch_regs_engine_hung(adev, false); in soc15_asic_mode1_reset()
476 static int soc15_asic_baco_reset(struct amdgpu_device *adev) in soc15_asic_baco_reset() argument
478 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_baco_reset()
483 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); in soc15_asic_baco_reset()
485 ret = amdgpu_dpm_baco_reset(adev); in soc15_asic_baco_reset()
491 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); in soc15_asic_baco_reset()
497 soc15_asic_reset_method(struct amdgpu_device *adev) in soc15_asic_reset_method() argument
500 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_reset_method()
508 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in soc15_asic_reset_method()
511 switch (adev->asic_type) { in soc15_asic_reset_method()
518 baco_reset = amdgpu_dpm_is_baco_supported(adev); in soc15_asic_reset_method()
521 if (adev->psp.sos_fw_version >= 0x80067) in soc15_asic_reset_method()
522 baco_reset = amdgpu_dpm_is_baco_supported(adev); in soc15_asic_reset_method()
528 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400) in soc15_asic_reset_method()
541 static int soc15_asic_reset(struct amdgpu_device *adev) in soc15_asic_reset() argument
544 if ((adev->apu_flags & AMD_APU_IS_RAVEN) && in soc15_asic_reset()
545 !(adev->apu_flags & AMD_APU_IS_RAVEN2)) in soc15_asic_reset()
548 switch (soc15_asic_reset_method(adev)) { in soc15_asic_reset()
550 dev_info(adev->dev, "BACO reset\n"); in soc15_asic_reset()
551 return soc15_asic_baco_reset(adev); in soc15_asic_reset()
553 dev_info(adev->dev, "MODE2 reset\n"); in soc15_asic_reset()
554 return amdgpu_dpm_mode2_reset(adev); in soc15_asic_reset()
556 dev_info(adev->dev, "MODE1 reset\n"); in soc15_asic_reset()
557 return soc15_asic_mode1_reset(adev); in soc15_asic_reset()
561 static bool soc15_supports_baco(struct amdgpu_device *adev) in soc15_supports_baco() argument
563 switch (adev->asic_type) { in soc15_supports_baco()
567 return amdgpu_dpm_is_baco_supported(adev); in soc15_supports_baco()
569 if (adev->psp.sos_fw_version >= 0x80067) in soc15_supports_baco()
570 return amdgpu_dpm_is_baco_supported(adev); in soc15_supports_baco()
583 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in soc15_set_uvd_clocks() argument
596 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in soc15_set_vce_clocks() argument
603 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) in soc15_pcie_gen3_enable() argument
605 if (pci_is_root_bus(adev->pdev->bus)) in soc15_pcie_gen3_enable()
611 if (adev->flags & AMD_IS_APU) in soc15_pcie_gen3_enable()
614 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | in soc15_pcie_gen3_enable()
621 static void soc15_program_aspm(struct amdgpu_device *adev) in soc15_program_aspm() argument
630 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, in soc15_enable_doorbell_aperture() argument
633 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); in soc15_enable_doorbell_aperture()
634 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); in soc15_enable_doorbell_aperture()
646 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) in soc15_get_rev_id() argument
648 return adev->nbio.funcs->get_rev_id(adev); in soc15_get_rev_id()
651 static void soc15_reg_base_init(struct amdgpu_device *adev) in soc15_reg_base_init() argument
656 switch (adev->asic_type) { in soc15_reg_base_init()
660 vega10_reg_base_init(adev); in soc15_reg_base_init()
666 r = amdgpu_discovery_reg_base_init(adev); in soc15_reg_base_init()
672 vega10_reg_base_init(adev); in soc15_reg_base_init()
675 vega20_reg_base_init(adev); in soc15_reg_base_init()
678 arct_reg_base_init(adev); in soc15_reg_base_init()
681 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); in soc15_reg_base_init()
686 void soc15_set_virt_ops(struct amdgpu_device *adev) in soc15_set_virt_ops() argument
688 adev->virt.ops = &xgpu_ai_virt_ops; in soc15_set_virt_ops()
693 soc15_reg_base_init(adev); in soc15_set_virt_ops()
696 int soc15_set_ip_blocks(struct amdgpu_device *adev) in soc15_set_ip_blocks() argument
699 if (!amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
700 soc15_reg_base_init(adev); in soc15_set_ip_blocks()
702 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) in soc15_set_ip_blocks()
703 adev->gmc.xgmi.supported = true; in soc15_set_ip_blocks()
705 if (adev->flags & AMD_IS_APU) { in soc15_set_ip_blocks()
706 adev->nbio.funcs = &nbio_v7_0_funcs; in soc15_set_ip_blocks()
707 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; in soc15_set_ip_blocks()
708 } else if (adev->asic_type == CHIP_VEGA20 || in soc15_set_ip_blocks()
709 adev->asic_type == CHIP_ARCTURUS) { in soc15_set_ip_blocks()
710 adev->nbio.funcs = &nbio_v7_4_funcs; in soc15_set_ip_blocks()
711 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; in soc15_set_ip_blocks()
713 adev->nbio.funcs = &nbio_v6_1_funcs; in soc15_set_ip_blocks()
714 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; in soc15_set_ip_blocks()
717 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) in soc15_set_ip_blocks()
718 adev->df.funcs = &df_v3_6_funcs; in soc15_set_ip_blocks()
720 adev->df.funcs = &df_v1_7_funcs; in soc15_set_ip_blocks()
722 adev->rev_id = soc15_get_rev_id(adev); in soc15_set_ip_blocks()
724 switch (adev->asic_type) { in soc15_set_ip_blocks()
728 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); in soc15_set_ip_blocks()
729 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); in soc15_set_ip_blocks()
732 if (amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
733 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { in soc15_set_ip_blocks()
734 if (adev->asic_type == CHIP_VEGA20) in soc15_set_ip_blocks()
735 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in soc15_set_ip_blocks()
737 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); in soc15_set_ip_blocks()
739 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); in soc15_set_ip_blocks()
741 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); in soc15_set_ip_blocks()
742 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { in soc15_set_ip_blocks()
743 if (adev->asic_type == CHIP_VEGA20) in soc15_set_ip_blocks()
744 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in soc15_set_ip_blocks()
746 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); in soc15_set_ip_blocks()
749 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); in soc15_set_ip_blocks()
750 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); in soc15_set_ip_blocks()
751 if (is_support_sw_smu(adev)) { in soc15_set_ip_blocks()
752 if (!amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
753 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in soc15_set_ip_blocks()
755 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in soc15_set_ip_blocks()
757 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
758 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in soc15_set_ip_blocks()
760 else if (amdgpu_device_has_dc_support(adev)) in soc15_set_ip_blocks()
761 amdgpu_device_ip_block_add(adev, &dm_ip_block); in soc15_set_ip_blocks()
763 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { in soc15_set_ip_blocks()
764 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); in soc15_set_ip_blocks()
765 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); in soc15_set_ip_blocks()
769 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); in soc15_set_ip_blocks()
770 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); in soc15_set_ip_blocks()
771 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); in soc15_set_ip_blocks()
772 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in soc15_set_ip_blocks()
773 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); in soc15_set_ip_blocks()
774 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); in soc15_set_ip_blocks()
775 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); in soc15_set_ip_blocks()
776 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in soc15_set_ip_blocks()
777 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
778 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in soc15_set_ip_blocks()
780 else if (amdgpu_device_has_dc_support(adev)) in soc15_set_ip_blocks()
781 amdgpu_device_ip_block_add(adev, &dm_ip_block); in soc15_set_ip_blocks()
783 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); in soc15_set_ip_blocks()
786 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); in soc15_set_ip_blocks()
787 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); in soc15_set_ip_blocks()
789 if (amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
790 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in soc15_set_ip_blocks()
791 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in soc15_set_ip_blocks()
792 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); in soc15_set_ip_blocks()
794 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); in soc15_set_ip_blocks()
795 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in soc15_set_ip_blocks()
796 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in soc15_set_ip_blocks()
799 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
800 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in soc15_set_ip_blocks()
801 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); in soc15_set_ip_blocks()
802 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); in soc15_set_ip_blocks()
803 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in soc15_set_ip_blocks()
805 if (amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
806 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in soc15_set_ip_blocks()
807 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); in soc15_set_ip_blocks()
809 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); in soc15_set_ip_blocks()
811 if (!amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
812 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); in soc15_set_ip_blocks()
815 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); in soc15_set_ip_blocks()
816 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); in soc15_set_ip_blocks()
817 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); in soc15_set_ip_blocks()
818 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in soc15_set_ip_blocks()
819 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); in soc15_set_ip_blocks()
820 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); in soc15_set_ip_blocks()
821 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); in soc15_set_ip_blocks()
822 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); in soc15_set_ip_blocks()
823 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
824 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in soc15_set_ip_blocks()
826 else if (amdgpu_device_has_dc_support(adev)) in soc15_set_ip_blocks()
827 amdgpu_device_ip_block_add(adev, &dm_ip_block); in soc15_set_ip_blocks()
829 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); in soc15_set_ip_blocks()
830 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); in soc15_set_ip_blocks()
839 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) in soc15_flush_hdp() argument
841 adev->nbio.funcs->hdp_flush(adev, ring); in soc15_flush_hdp()
844 static void soc15_invalidate_hdp(struct amdgpu_device *adev, in soc15_invalidate_hdp() argument
854 static bool soc15_need_full_reset(struct amdgpu_device *adev) in soc15_need_full_reset() argument
860 static void vega20_reset_hdp_ras_error_count(struct amdgpu_device *adev) in vega20_reset_hdp_ras_error_count() argument
862 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP)) in vega20_reset_hdp_ras_error_count()
868 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, in soc15_get_pcie_usage() argument
878 if (adev->flags & AMD_IS_APU) in soc15_get_pcie_usage()
915 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, in vega20_get_pcie_usage() argument
925 if (adev->flags & AMD_IS_APU) in vega20_get_pcie_usage()
964 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) in soc15_need_reset_on_init() argument
971 if (!amdgpu_passthrough(adev)) in soc15_need_reset_on_init()
974 if (adev->flags & AMD_IS_APU) in soc15_need_reset_on_init()
987 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) in soc15_get_pcie_replay_count() argument
999 static void soc15_pre_asic_init(struct amdgpu_device *adev) in soc15_pre_asic_init() argument
1001 gmc_v9_0_restore_registers(adev); in soc15_pre_asic_init()
1054 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_early_init() local
1056 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; in soc15_common_early_init()
1057 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; in soc15_common_early_init()
1058 adev->smc_rreg = NULL; in soc15_common_early_init()
1059 adev->smc_wreg = NULL; in soc15_common_early_init()
1060 adev->pcie_rreg = &soc15_pcie_rreg; in soc15_common_early_init()
1061 adev->pcie_wreg = &soc15_pcie_wreg; in soc15_common_early_init()
1062 adev->pcie_rreg64 = &soc15_pcie_rreg64; in soc15_common_early_init()
1063 adev->pcie_wreg64 = &soc15_pcie_wreg64; in soc15_common_early_init()
1064 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; in soc15_common_early_init()
1065 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; in soc15_common_early_init()
1066 adev->didt_rreg = &soc15_didt_rreg; in soc15_common_early_init()
1067 adev->didt_wreg = &soc15_didt_wreg; in soc15_common_early_init()
1068 adev->gc_cac_rreg = &soc15_gc_cac_rreg; in soc15_common_early_init()
1069 adev->gc_cac_wreg = &soc15_gc_cac_wreg; in soc15_common_early_init()
1070 adev->se_cac_rreg = &soc15_se_cac_rreg; in soc15_common_early_init()
1071 adev->se_cac_wreg = &soc15_se_cac_wreg; in soc15_common_early_init()
1074 adev->external_rev_id = 0xFF; in soc15_common_early_init()
1075 switch (adev->asic_type) { in soc15_common_early_init()
1077 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1078 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1097 adev->pg_flags = 0; in soc15_common_early_init()
1098 adev->external_rev_id = 0x1; in soc15_common_early_init()
1101 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1102 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1120 adev->pg_flags = 0; in soc15_common_early_init()
1121 adev->external_rev_id = adev->rev_id + 0x14; in soc15_common_early_init()
1124 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1125 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1143 adev->pg_flags = 0; in soc15_common_early_init()
1144 adev->external_rev_id = adev->rev_id + 0x28; in soc15_common_early_init()
1147 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1148 if (adev->pdev->device == 0x15dd) in soc15_common_early_init()
1149 adev->apu_flags |= AMD_APU_IS_RAVEN; in soc15_common_early_init()
1150 if (adev->pdev->device == 0x15d8) in soc15_common_early_init()
1151 adev->apu_flags |= AMD_APU_IS_PICASSO; in soc15_common_early_init()
1152 if (adev->rev_id >= 0x8) in soc15_common_early_init()
1153 adev->apu_flags |= AMD_APU_IS_RAVEN2; in soc15_common_early_init()
1155 if (adev->apu_flags & AMD_APU_IS_RAVEN2) in soc15_common_early_init()
1156 adev->external_rev_id = adev->rev_id + 0x79; in soc15_common_early_init()
1157 else if (adev->apu_flags & AMD_APU_IS_PICASSO) in soc15_common_early_init()
1158 adev->external_rev_id = adev->rev_id + 0x41; in soc15_common_early_init()
1159 else if (adev->rev_id == 1) in soc15_common_early_init()
1160 adev->external_rev_id = adev->rev_id + 0x20; in soc15_common_early_init()
1162 adev->external_rev_id = adev->rev_id + 0x01; in soc15_common_early_init()
1164 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { in soc15_common_early_init()
1165 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1181 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; in soc15_common_early_init()
1182 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { in soc15_common_early_init()
1183 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1201 adev->pg_flags = AMD_PG_SUPPORT_SDMA | in soc15_common_early_init()
1204 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1224 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; in soc15_common_early_init()
1228 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1229 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1243 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; in soc15_common_early_init()
1244 adev->external_rev_id = adev->rev_id + 0x32; in soc15_common_early_init()
1247 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1248 if ((adev->pdev->device == 0x1636) || in soc15_common_early_init()
1249 (adev->pdev->device == 0x164c)) in soc15_common_early_init()
1250 adev->apu_flags |= AMD_APU_IS_RENOIR; in soc15_common_early_init()
1252 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE; in soc15_common_early_init()
1254 if (adev->apu_flags & AMD_APU_IS_RENOIR) in soc15_common_early_init()
1255 adev->external_rev_id = adev->rev_id + 0x91; in soc15_common_early_init()
1257 adev->external_rev_id = adev->rev_id + 0xa1; in soc15_common_early_init()
1258 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1278 adev->pg_flags = AMD_PG_SUPPORT_SDMA | in soc15_common_early_init()
1288 if (amdgpu_sriov_vf(adev)) { in soc15_common_early_init()
1289 amdgpu_virt_init_setting(adev); in soc15_common_early_init()
1290 xgpu_ai_mailbox_set_irq_funcs(adev); in soc15_common_early_init()
1298 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_late_init() local
1301 if (amdgpu_sriov_vf(adev)) in soc15_common_late_init()
1302 xgpu_ai_mailbox_get_irq(adev); in soc15_common_late_init()
1304 if (adev->asic_funcs && in soc15_common_late_init()
1305 adev->asic_funcs->reset_hdp_ras_error_count) in soc15_common_late_init()
1306 adev->asic_funcs->reset_hdp_ras_error_count(adev); in soc15_common_late_init()
1308 if (adev->nbio.funcs->ras_late_init) in soc15_common_late_init()
1309 r = adev->nbio.funcs->ras_late_init(adev); in soc15_common_late_init()
1316 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_sw_init() local
1318 if (amdgpu_sriov_vf(adev)) in soc15_common_sw_init()
1319 xgpu_ai_mailbox_add_irq_id(adev); in soc15_common_sw_init()
1321 adev->df.funcs->sw_init(adev); in soc15_common_sw_init()
1328 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_sw_fini() local
1330 amdgpu_nbio_ras_fini(adev); in soc15_common_sw_fini()
1331 adev->df.funcs->sw_fini(adev); in soc15_common_sw_fini()
1335 static void soc15_doorbell_range_init(struct amdgpu_device *adev) in soc15_doorbell_range_init() argument
1341 if (!amdgpu_sriov_vf(adev)) { in soc15_doorbell_range_init()
1342 for (i = 0; i < adev->sdma.num_instances; i++) { in soc15_doorbell_range_init()
1343 ring = &adev->sdma.instance[i].ring; in soc15_doorbell_range_init()
1344 adev->nbio.funcs->sdma_doorbell_range(adev, i, in soc15_doorbell_range_init()
1346 adev->doorbell_index.sdma_doorbell_range); in soc15_doorbell_range_init()
1349 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, in soc15_doorbell_range_init()
1350 adev->irq.ih.doorbell_index); in soc15_doorbell_range_init()
1356 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_hw_init() local
1359 soc15_pcie_gen3_enable(adev); in soc15_common_hw_init()
1361 soc15_program_aspm(adev); in soc15_common_hw_init()
1363 adev->nbio.funcs->init_registers(adev); in soc15_common_hw_init()
1368 if (adev->nbio.funcs->remap_hdp_registers) in soc15_common_hw_init()
1369 adev->nbio.funcs->remap_hdp_registers(adev); in soc15_common_hw_init()
1372 soc15_enable_doorbell_aperture(adev, true); in soc15_common_hw_init()
1378 soc15_doorbell_range_init(adev); in soc15_common_hw_init()
1385 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_hw_fini() local
1388 soc15_enable_doorbell_aperture(adev, false); in soc15_common_hw_fini()
1389 if (amdgpu_sriov_vf(adev)) in soc15_common_hw_fini()
1390 xgpu_ai_mailbox_put_irq(adev); in soc15_common_hw_fini()
1392 if (adev->nbio.ras_if && in soc15_common_hw_fini()
1393 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { in soc15_common_hw_fini()
1394 if (adev->nbio.funcs->init_ras_controller_interrupt) in soc15_common_hw_fini()
1395 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); in soc15_common_hw_fini()
1396 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) in soc15_common_hw_fini()
1397 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); in soc15_common_hw_fini()
1405 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_suspend() local
1407 return soc15_common_hw_fini(adev); in soc15_common_suspend()
1412 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_resume() local
1414 return soc15_common_hw_init(adev); in soc15_common_resume()
1432 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable) in soc15_update_hdp_light_sleep() argument
1436 if (adev->asic_type == CHIP_VEGA20 || in soc15_update_hdp_light_sleep()
1437 adev->asic_type == CHIP_ARCTURUS || in soc15_update_hdp_light_sleep()
1438 adev->asic_type == CHIP_RENOIR) { in soc15_update_hdp_light_sleep()
1441 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) in soc15_update_hdp_light_sleep()
1457 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) in soc15_update_hdp_light_sleep()
1467 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) in soc15_update_drm_clock_gating() argument
1473 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) in soc15_update_drm_clock_gating()
1496 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) in soc15_update_drm_light_sleep() argument
1502 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) in soc15_update_drm_light_sleep()
1511 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, in soc15_update_rom_medium_grain_clock_gating() argument
1518 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) in soc15_update_rom_medium_grain_clock_gating()
1532 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_set_clockgating_state() local
1534 if (amdgpu_sriov_vf(adev)) in soc15_common_set_clockgating_state()
1537 switch (adev->asic_type) { in soc15_common_set_clockgating_state()
1541 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1543 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
1545 soc15_update_hdp_light_sleep(adev, in soc15_common_set_clockgating_state()
1547 soc15_update_drm_clock_gating(adev, in soc15_common_set_clockgating_state()
1549 soc15_update_drm_light_sleep(adev, in soc15_common_set_clockgating_state()
1551 soc15_update_rom_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1553 adev->df.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1558 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1560 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
1562 soc15_update_hdp_light_sleep(adev, in soc15_common_set_clockgating_state()
1564 soc15_update_drm_clock_gating(adev, in soc15_common_set_clockgating_state()
1566 soc15_update_drm_light_sleep(adev, in soc15_common_set_clockgating_state()
1568 soc15_update_rom_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1572 soc15_update_hdp_light_sleep(adev, in soc15_common_set_clockgating_state()
1583 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_get_clockgating_state() local
1586 if (amdgpu_sriov_vf(adev)) in soc15_common_get_clockgating_state()
1589 adev->nbio.funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()
1611 adev->df.funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()