Lines Matching refs:adev
70 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) in nv_pcie_rreg() argument
73 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg()
74 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg()
76 return amdgpu_device_indirect_rreg(adev, address, data, reg); in nv_pcie_rreg()
79 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_pcie_wreg() argument
83 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg()
84 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg()
86 amdgpu_device_indirect_wreg(adev, address, data, reg, v); in nv_pcie_wreg()
89 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) in nv_pcie_rreg64() argument
92 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg64()
93 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg64()
95 return amdgpu_device_indirect_rreg64(adev, address, data, reg); in nv_pcie_rreg64()
98 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) in nv_pcie_wreg64() argument
102 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg64()
103 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg64()
105 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); in nv_pcie_wreg64()
108 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) in nv_didt_rreg() argument
116 spin_lock_irqsave(&adev->didt_idx_lock, flags); in nv_didt_rreg()
119 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in nv_didt_rreg()
123 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_didt_wreg() argument
130 spin_lock_irqsave(&adev->didt_idx_lock, flags); in nv_didt_wreg()
133 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in nv_didt_wreg()
136 static u32 nv_get_config_memsize(struct amdgpu_device *adev) in nv_get_config_memsize() argument
138 return adev->nbio.funcs->get_memsize(adev); in nv_get_config_memsize()
141 static u32 nv_get_xclk(struct amdgpu_device *adev) in nv_get_xclk() argument
143 return adev->clock.spll.reference_freq; in nv_get_xclk()
147 void nv_grbm_select(struct amdgpu_device *adev, in nv_grbm_select() argument
159 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) in nv_vga_set_state() argument
164 static bool nv_read_disabled_bios(struct amdgpu_device *adev) in nv_read_disabled_bios() argument
170 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, in nv_read_bios_from_rom() argument
181 if (adev->flags & AMD_IS_APU) in nv_read_bios_from_rom()
218 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in nv_read_indexed_register() argument
223 mutex_lock(&adev->grbm_idx_mutex); in nv_read_indexed_register()
225 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in nv_read_indexed_register()
230 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in nv_read_indexed_register()
231 mutex_unlock(&adev->grbm_idx_mutex); in nv_read_indexed_register()
235 static uint32_t nv_get_register_value(struct amdgpu_device *adev, in nv_get_register_value() argument
240 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
243 return adev->gfx.config.gb_addr_config; in nv_get_register_value()
248 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, in nv_read_register() argument
258 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) in nv_read_register()
261 *value = nv_get_register_value(adev, in nv_read_register()
269 static int nv_asic_mode1_reset(struct amdgpu_device *adev) in nv_asic_mode1_reset() argument
274 amdgpu_atombios_scratch_regs_engine_hung(adev, true); in nv_asic_mode1_reset()
277 pci_clear_master(adev->pdev); in nv_asic_mode1_reset()
279 amdgpu_device_cache_pci_state(adev->pdev); in nv_asic_mode1_reset()
281 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { in nv_asic_mode1_reset()
282 dev_info(adev->dev, "GPU smu mode1 reset\n"); in nv_asic_mode1_reset()
283 ret = amdgpu_dpm_mode1_reset(adev); in nv_asic_mode1_reset()
285 dev_info(adev->dev, "GPU psp mode1 reset\n"); in nv_asic_mode1_reset()
286 ret = psp_gpu_reset(adev); in nv_asic_mode1_reset()
290 dev_err(adev->dev, "GPU mode1 reset failed\n"); in nv_asic_mode1_reset()
291 amdgpu_device_load_pci_state(adev->pdev); in nv_asic_mode1_reset()
294 for (i = 0; i < adev->usec_timeout; i++) { in nv_asic_mode1_reset()
295 u32 memsize = adev->nbio.funcs->get_memsize(adev); in nv_asic_mode1_reset()
302 amdgpu_atombios_scratch_regs_engine_hung(adev, false); in nv_asic_mode1_reset()
307 static bool nv_asic_supports_baco(struct amdgpu_device *adev) in nv_asic_supports_baco() argument
309 struct smu_context *smu = &adev->smu; in nv_asic_supports_baco()
318 nv_asic_reset_method(struct amdgpu_device *adev) in nv_asic_reset_method() argument
320 struct smu_context *smu = &adev->smu; in nv_asic_reset_method()
327 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in nv_asic_reset_method()
330 switch (adev->asic_type) { in nv_asic_reset_method()
342 static int nv_asic_reset(struct amdgpu_device *adev) in nv_asic_reset() argument
345 struct smu_context *smu = &adev->smu; in nv_asic_reset()
347 if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { in nv_asic_reset()
348 dev_info(adev->dev, "BACO reset\n"); in nv_asic_reset()
357 dev_info(adev->dev, "MODE1 reset\n"); in nv_asic_reset()
358 ret = nv_asic_mode1_reset(adev); in nv_asic_reset()
364 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in nv_set_uvd_clocks() argument
370 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in nv_set_vce_clocks() argument
376 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) in nv_pcie_gen3_enable() argument
378 if (pci_is_root_bus(adev->pdev->bus)) in nv_pcie_gen3_enable()
384 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | in nv_pcie_gen3_enable()
391 static void nv_program_aspm(struct amdgpu_device *adev) in nv_program_aspm() argument
400 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, in nv_enable_doorbell_aperture() argument
403 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); in nv_enable_doorbell_aperture()
404 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); in nv_enable_doorbell_aperture()
416 static int nv_reg_base_init(struct amdgpu_device *adev) in nv_reg_base_init() argument
421 r = amdgpu_discovery_reg_base_init(adev); in nv_reg_base_init()
432 switch (adev->asic_type) { in nv_reg_base_init()
434 navi10_reg_base_init(adev); in nv_reg_base_init()
437 navi14_reg_base_init(adev); in nv_reg_base_init()
440 navi12_reg_base_init(adev); in nv_reg_base_init()
444 sienna_cichlid_reg_base_init(adev); in nv_reg_base_init()
453 void nv_set_virt_ops(struct amdgpu_device *adev) in nv_set_virt_ops() argument
455 adev->virt.ops = &xgpu_nv_virt_ops; in nv_set_virt_ops()
468 int nv_set_ip_blocks(struct amdgpu_device *adev) in nv_set_ip_blocks() argument
472 adev->nbio.funcs = &nbio_v2_3_funcs; in nv_set_ip_blocks()
473 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; in nv_set_ip_blocks()
475 if (adev->asic_type == CHIP_SIENNA_CICHLID) in nv_set_ip_blocks()
476 adev->gmc.xgmi.supported = true; in nv_set_ip_blocks()
479 r = nv_reg_base_init(adev); in nv_set_ip_blocks()
483 switch (adev->asic_type) { in nv_set_ip_blocks()
486 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
487 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
488 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
489 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
490 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && in nv_set_ip_blocks()
491 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
492 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
493 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
494 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in nv_set_ip_blocks()
496 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
497 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
499 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
500 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); in nv_set_ip_blocks()
501 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && in nv_set_ip_blocks()
502 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
503 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
504 if (!nv_is_headless_sku(adev->pdev)) in nv_set_ip_blocks()
505 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); in nv_set_ip_blocks()
506 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); in nv_set_ip_blocks()
507 if (adev->enable_mes) in nv_set_ip_blocks()
508 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); in nv_set_ip_blocks()
511 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
512 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
513 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
514 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
515 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) in nv_set_ip_blocks()
516 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
517 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
518 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in nv_set_ip_blocks()
520 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
521 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
523 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
524 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); in nv_set_ip_blocks()
525 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && in nv_set_ip_blocks()
526 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
527 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
528 if (!nv_is_headless_sku(adev->pdev)) in nv_set_ip_blocks()
529 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); in nv_set_ip_blocks()
530 if (!amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
531 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); in nv_set_ip_blocks()
534 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
535 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
536 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
537 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
538 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
539 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && in nv_set_ip_blocks()
540 is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
541 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
542 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
543 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in nv_set_ip_blocks()
545 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
546 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
548 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
549 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); in nv_set_ip_blocks()
550 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); in nv_set_ip_blocks()
551 if (!amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
552 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); in nv_set_ip_blocks()
554 if (adev->enable_mes) in nv_set_ip_blocks()
555 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); in nv_set_ip_blocks()
558 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); in nv_set_ip_blocks()
559 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); in nv_set_ip_blocks()
560 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); in nv_set_ip_blocks()
561 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) in nv_set_ip_blocks()
562 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); in nv_set_ip_blocks()
563 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && in nv_set_ip_blocks()
564 is_support_sw_smu(adev)) in nv_set_ip_blocks()
565 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
566 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
567 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in nv_set_ip_blocks()
569 else if (amdgpu_device_has_dc_support(adev)) in nv_set_ip_blocks()
570 amdgpu_device_ip_block_add(adev, &dm_ip_block); in nv_set_ip_blocks()
572 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); in nv_set_ip_blocks()
573 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); in nv_set_ip_blocks()
574 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); in nv_set_ip_blocks()
575 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); in nv_set_ip_blocks()
576 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && in nv_set_ip_blocks()
577 is_support_sw_smu(adev)) in nv_set_ip_blocks()
578 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); in nv_set_ip_blocks()
587 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) in nv_get_rev_id() argument
589 return adev->nbio.funcs->get_rev_id(adev); in nv_get_rev_id()
592 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) in nv_flush_hdp() argument
594 adev->nbio.funcs->hdp_flush(adev, ring); in nv_flush_hdp()
597 static void nv_invalidate_hdp(struct amdgpu_device *adev, in nv_invalidate_hdp() argument
608 static bool nv_need_full_reset(struct amdgpu_device *adev) in nv_need_full_reset() argument
613 static bool nv_need_reset_on_init(struct amdgpu_device *adev) in nv_need_reset_on_init() argument
617 if (adev->flags & AMD_IS_APU) in nv_need_reset_on_init()
630 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) in nv_get_pcie_replay_count() argument
640 static void nv_init_doorbell_index(struct amdgpu_device *adev) in nv_init_doorbell_index() argument
642 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; in nv_init_doorbell_index()
643 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; in nv_init_doorbell_index()
644 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; in nv_init_doorbell_index()
645 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; in nv_init_doorbell_index()
646 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; in nv_init_doorbell_index()
647 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; in nv_init_doorbell_index()
648 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; in nv_init_doorbell_index()
649 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; in nv_init_doorbell_index()
650 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; in nv_init_doorbell_index()
651 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; in nv_init_doorbell_index()
652 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; in nv_init_doorbell_index()
653 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; in nv_init_doorbell_index()
654 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; in nv_init_doorbell_index()
655 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; in nv_init_doorbell_index()
656 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; in nv_init_doorbell_index()
657 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; in nv_init_doorbell_index()
658 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; in nv_init_doorbell_index()
659 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; in nv_init_doorbell_index()
660 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; in nv_init_doorbell_index()
661 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; in nv_init_doorbell_index()
662 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; in nv_init_doorbell_index()
663 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; in nv_init_doorbell_index()
664 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; in nv_init_doorbell_index()
665 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; in nv_init_doorbell_index()
666 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; in nv_init_doorbell_index()
668 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; in nv_init_doorbell_index()
669 adev->doorbell_index.sdma_doorbell_range = 20; in nv_init_doorbell_index()
672 static void nv_pre_asic_init(struct amdgpu_device *adev) in nv_pre_asic_init() argument
701 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_early_init() local
703 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; in nv_common_early_init()
704 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; in nv_common_early_init()
705 adev->smc_rreg = NULL; in nv_common_early_init()
706 adev->smc_wreg = NULL; in nv_common_early_init()
707 adev->pcie_rreg = &nv_pcie_rreg; in nv_common_early_init()
708 adev->pcie_wreg = &nv_pcie_wreg; in nv_common_early_init()
709 adev->pcie_rreg64 = &nv_pcie_rreg64; in nv_common_early_init()
710 adev->pcie_wreg64 = &nv_pcie_wreg64; in nv_common_early_init()
713 adev->uvd_ctx_rreg = NULL; in nv_common_early_init()
714 adev->uvd_ctx_wreg = NULL; in nv_common_early_init()
716 adev->didt_rreg = &nv_didt_rreg; in nv_common_early_init()
717 adev->didt_wreg = &nv_didt_wreg; in nv_common_early_init()
719 adev->asic_funcs = &nv_asic_funcs; in nv_common_early_init()
721 adev->rev_id = nv_get_rev_id(adev); in nv_common_early_init()
722 adev->external_rev_id = 0xff; in nv_common_early_init()
723 switch (adev->asic_type) { in nv_common_early_init()
725 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
740 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
744 adev->external_rev_id = adev->rev_id + 0x1; in nv_common_early_init()
747 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
762 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
765 adev->external_rev_id = adev->rev_id + 20; in nv_common_early_init()
768 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
784 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
792 if (amdgpu_sriov_vf(adev)) in nv_common_early_init()
793 adev->rev_id = 0; in nv_common_early_init()
794 adev->external_rev_id = adev->rev_id + 0xa; in nv_common_early_init()
797 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
807 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
812 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
814 adev->cg_flags = 0; in nv_common_early_init()
815 adev->pg_flags = 0; in nv_common_early_init()
817 adev->external_rev_id = adev->rev_id + 0x28; in nv_common_early_init()
820 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in nv_common_early_init()
830 adev->pg_flags = AMD_PG_SUPPORT_VCN | in nv_common_early_init()
835 adev->external_rev_id = adev->rev_id + 0x32; in nv_common_early_init()
843 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
844 amdgpu_virt_init_setting(adev); in nv_common_early_init()
845 xgpu_nv_mailbox_set_irq_funcs(adev); in nv_common_early_init()
853 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_late_init() local
855 if (amdgpu_sriov_vf(adev)) in nv_common_late_init()
856 xgpu_nv_mailbox_get_irq(adev); in nv_common_late_init()
863 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_sw_init() local
865 if (amdgpu_sriov_vf(adev)) in nv_common_sw_init()
866 xgpu_nv_mailbox_add_irq_id(adev); in nv_common_sw_init()
878 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_hw_init() local
881 nv_pcie_gen3_enable(adev); in nv_common_hw_init()
883 nv_program_aspm(adev); in nv_common_hw_init()
885 adev->nbio.funcs->init_registers(adev); in nv_common_hw_init()
890 if (adev->nbio.funcs->remap_hdp_registers) in nv_common_hw_init()
891 adev->nbio.funcs->remap_hdp_registers(adev); in nv_common_hw_init()
893 nv_enable_doorbell_aperture(adev, true); in nv_common_hw_init()
900 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_hw_fini() local
903 nv_enable_doorbell_aperture(adev, false); in nv_common_hw_fini()
910 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_suspend() local
912 return nv_common_hw_fini(adev); in nv_common_suspend()
917 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_resume() local
919 return nv_common_hw_init(adev); in nv_common_resume()
937 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, in nv_update_hdp_mem_power_gating() argument
943 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | in nv_update_hdp_mem_power_gating()
980 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { in nv_update_hdp_mem_power_gating()
987 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { in nv_update_hdp_mem_power_gating()
994 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { in nv_update_hdp_mem_power_gating()
1006 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | in nv_update_hdp_mem_power_gating()
1020 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, in nv_update_hdp_clock_gating() argument
1025 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) in nv_update_hdp_clock_gating()
1054 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_set_clockgating_state() local
1056 if (amdgpu_sriov_vf(adev)) in nv_common_set_clockgating_state()
1059 switch (adev->asic_type) { in nv_common_set_clockgating_state()
1065 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in nv_common_set_clockgating_state()
1067 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in nv_common_set_clockgating_state()
1069 nv_update_hdp_mem_power_gating(adev, in nv_common_set_clockgating_state()
1071 nv_update_hdp_clock_gating(adev, in nv_common_set_clockgating_state()
1089 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in nv_common_get_clockgating_state() local
1092 if (amdgpu_sriov_vf(adev)) in nv_common_get_clockgating_state()
1095 adev->nbio.funcs->get_clockgating_state(adev, flags); in nv_common_get_clockgating_state()