1060 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)  argument
1061 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)  argument
1063 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))  argument
1064 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))  argument
1066 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))  argument
1067 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))  argument
1069 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)  argument
1070 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg…  argument
1071 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)  argument
1074 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))  argument
1075 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))  argument
1076 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))  argument
1077 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))  argument
1078 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))  argument
1079 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))  argument
1080 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))  argument
1081 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))  argument
1082 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))  argument
1083 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))  argument
1084 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))  argument
1085 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))  argument
1086 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))  argument
1087 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))  argument
1088 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))  argument
1089 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))  argument
1090 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))  argument
1091 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))  argument
1092 #define WREG32_P(reg, val, mask)				\  argument
1099 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)  argument
1100 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))  argument
1101 #define WREG32_PLL_P(reg, val, mask)				\  argument
1117 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev),…  argument
1118 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))  argument
1119 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))  argument
1121 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT  argument
1122 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK  argument
1124 #define REG_SET_FIELD(orig_val, reg, field, field_val)			\  argument
1128 #define REG_GET_FIELD(value, reg, field)				\  argument
1131 #define WREG32_FIELD(reg, field, val)	\  argument
1134 #define WREG32_FIELD_OFFSET(reg, offset, field, val)	\  argument