Lines Matching full:bank
77 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, in rockchip_gpio_writel() argument
80 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
82 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel()
88 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, in rockchip_gpio_readl() argument
91 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl()
94 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_readl()
102 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_writel_bit() argument
106 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel_bit()
109 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_gpio_writel_bit()
124 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_readl_bit() argument
127 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl_bit()
130 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_gpio_readl_bit()
144 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); in rockchip_gpio_get_direction() local
147 data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr); in rockchip_gpio_get_direction()
157 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); in rockchip_gpio_set_direction() local
161 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_gpio_set_direction()
162 rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr); in rockchip_gpio_set_direction()
163 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_gpio_set_direction()
171 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); in rockchip_gpio_set() local
174 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_gpio_set()
175 rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr); in rockchip_gpio_set()
176 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_gpio_set()
181 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); in rockchip_gpio_get() local
184 data = readl(bank->reg_base + bank->gpio_regs->ext_port); in rockchip_gpio_get()
195 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); in rockchip_gpio_set_debounce() local
196 const struct rockchip_gpio_regs *reg = bank->gpio_regs; in rockchip_gpio_set_debounce()
202 if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) { in rockchip_gpio_set_debounce()
204 freq = clk_get_rate(bank->db_clk); in rockchip_gpio_set_debounce()
217 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_gpio_set_debounce()
223 cur_div_reg = readl(bank->reg_base + in rockchip_gpio_set_debounce()
226 writel(div_reg, bank->reg_base + in rockchip_gpio_set_debounce()
228 rockchip_gpio_writel_bit(bank, offset, 1, in rockchip_gpio_set_debounce()
232 rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce); in rockchip_gpio_set_debounce()
235 rockchip_gpio_writel_bit(bank, offset, 0, in rockchip_gpio_set_debounce()
238 rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce); in rockchip_gpio_set_debounce()
241 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_gpio_set_debounce()
246 clk_prepare_enable(bank->db_clk); in rockchip_gpio_set_debounce()
248 clk_disable_unprepare(bank->db_clk); in rockchip_gpio_set_debounce()
305 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); in rockchip_gpio_to_irq() local
308 if (!bank->domain) in rockchip_gpio_to_irq()
311 virq = irq_create_mapping(bank->domain, offset); in rockchip_gpio_to_irq()
332 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); in rockchip_irq_demux() local
335 dev_dbg(bank->dev, "got irq for bank %s\n", bank->name); in rockchip_irq_demux()
339 pend = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status); in rockchip_irq_demux()
346 virq = irq_find_mapping(bank->domain, irq); in rockchip_irq_demux()
349 dev_err(bank->dev, "unmapped irq %d\n", irq); in rockchip_irq_demux()
353 dev_dbg(bank->dev, "handling irq %d\n", irq); in rockchip_irq_demux()
359 if (bank->toggle_edge_mode & BIT(irq)) { in rockchip_irq_demux()
363 data = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
364 bank->gpio_regs->ext_port); in rockchip_irq_demux()
366 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_demux()
368 polarity = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
369 bank->gpio_regs->int_polarity); in rockchip_irq_demux()
375 bank->reg_base + in rockchip_irq_demux()
376 bank->gpio_regs->int_polarity); in rockchip_irq_demux()
378 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_demux()
381 data = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
382 bank->gpio_regs->ext_port); in rockchip_irq_demux()
395 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_set_type() local
403 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_set_type()
405 rockchip_gpio_writel_bit(bank, d->hwirq, 0, in rockchip_irq_set_type()
406 bank->gpio_regs->port_ddr); in rockchip_irq_set_type()
408 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
415 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_set_type()
417 level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type); in rockchip_irq_set_type()
418 polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity); in rockchip_irq_set_type()
422 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_irq_set_type()
423 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
424 rockchip_gpio_writel_bit(bank, d->hwirq, 1, in rockchip_irq_set_type()
425 bank->gpio_regs->int_bothedge); in rockchip_irq_set_type()
428 bank->toggle_edge_mode |= mask; in rockchip_irq_set_type()
435 data = readl(bank->reg_base + bank->gpio_regs->ext_port); in rockchip_irq_set_type()
443 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
448 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
453 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
458 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
467 rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type); in rockchip_irq_set_type()
468 rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity); in rockchip_irq_set_type()
470 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
478 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_suspend() local
480 bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask); in rockchip_irq_suspend()
481 irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask); in rockchip_irq_suspend()
487 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_resume() local
489 irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask); in rockchip_irq_resume()
502 static int rockchip_interrupts_register(struct rockchip_pin_bank *bank) in rockchip_interrupts_register() argument
508 bank->domain = irq_domain_create_linear(dev_fwnode(bank->dev), 32, in rockchip_interrupts_register()
510 if (!bank->domain) { in rockchip_interrupts_register()
511 dev_warn(bank->dev, "could not init irq domain for bank %s\n", in rockchip_interrupts_register()
512 bank->name); in rockchip_interrupts_register()
516 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, in rockchip_interrupts_register()
521 dev_err(bank->dev, "could not alloc generic chips for bank %s\n", in rockchip_interrupts_register()
522 bank->name); in rockchip_interrupts_register()
523 irq_domain_remove(bank->domain); in rockchip_interrupts_register()
527 gc = irq_get_domain_generic_chip(bank->domain, 0); in rockchip_interrupts_register()
528 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_interrupts_register()
533 gc->reg_base = bank->reg_base; in rockchip_interrupts_register()
534 gc->private = bank; in rockchip_interrupts_register()
535 gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask; in rockchip_interrupts_register()
536 gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi; in rockchip_interrupts_register()
546 gc->wake_enabled = IRQ_MSK(bank->nr_pins); in rockchip_interrupts_register()
553 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask); in rockchip_interrupts_register()
554 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi); in rockchip_interrupts_register()
555 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en); in rockchip_interrupts_register()
558 irq_set_chained_handler_and_data(bank->irq, in rockchip_interrupts_register()
559 rockchip_irq_demux, bank); in rockchip_interrupts_register()
564 static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank) in rockchip_gpiolib_register() argument
569 bank->gpio_chip = rockchip_gpiolib_chip; in rockchip_gpiolib_register()
571 gc = &bank->gpio_chip; in rockchip_gpiolib_register()
572 gc->base = bank->pin_base; in rockchip_gpiolib_register()
573 gc->ngpio = bank->nr_pins; in rockchip_gpiolib_register()
574 gc->label = bank->name; in rockchip_gpiolib_register()
575 gc->parent = bank->dev; in rockchip_gpiolib_register()
578 gc->base = GPIO_MAX_PINS * bank->bank_num; in rockchip_gpiolib_register()
582 gc->label = kasprintf(GFP_KERNEL, "gpio%d", bank->bank_num); in rockchip_gpiolib_register()
587 ret = gpiochip_add_data(gc, bank); in rockchip_gpiolib_register()
589 dev_err(bank->dev, "failed to add gpiochip %s, %d\n", in rockchip_gpiolib_register()
594 ret = rockchip_interrupts_register(bank); in rockchip_gpiolib_register()
596 dev_err(bank->dev, "failed to register interrupt, %d\n", ret); in rockchip_gpiolib_register()
603 gpiochip_remove(&bank->gpio_chip); in rockchip_gpiolib_register()
608 static void rockchip_gpio_get_ver(struct rockchip_pin_bank *bank) in rockchip_gpio_get_ver() argument
610 int id = readl(bank->reg_base + gpio_regs_v2.version_id); in rockchip_gpio_get_ver()
614 bank->gpio_regs = &gpio_regs_v2; in rockchip_gpio_get_ver()
615 bank->gpio_type = GPIO_TYPE_V2; in rockchip_gpio_get_ver()
617 bank->gpio_regs = &gpio_regs_v1; in rockchip_gpio_get_ver()
618 bank->gpio_type = GPIO_TYPE_V1; in rockchip_gpio_get_ver()
626 struct rockchip_pin_bank *bank; in rockchip_gpio_find_bank() local
630 bank = info->ctrl->pin_banks; in rockchip_gpio_find_bank()
631 for (i = 0; i < info->ctrl->nr_banks; i++, bank++) { in rockchip_gpio_find_bank()
632 if (bank->bank_num == id) { in rockchip_gpio_find_bank()
638 return found ? bank : NULL; in rockchip_gpio_find_bank()
688 struct rockchip_pin_bank *bank = NULL; in rockchip_gpio_probe() local
706 bank = rockchip_gpio_find_bank(pctldev, bank_id); in rockchip_gpio_probe()
707 if (!bank) in rockchip_gpio_probe()
711 if (!bank) { in rockchip_gpio_probe()
712 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); in rockchip_gpio_probe()
713 if (!bank) in rockchip_gpio_probe()
717 bank->bank_num = bank_id; in rockchip_gpio_probe()
718 bank->dev = dev; in rockchip_gpio_probe()
720 bank->reg_base = devm_platform_ioremap_resource(pdev, 0); in rockchip_gpio_probe()
721 if (IS_ERR(bank->reg_base)) in rockchip_gpio_probe()
722 return PTR_ERR(bank->reg_base); in rockchip_gpio_probe()
724 bank->irq = platform_get_irq(pdev, 0); in rockchip_gpio_probe()
725 if (bank->irq < 0) in rockchip_gpio_probe()
726 return bank->irq; in rockchip_gpio_probe()
728 raw_spin_lock_init(&bank->slock); in rockchip_gpio_probe()
731 bank->clk = devm_clk_get(dev, "bus"); in rockchip_gpio_probe()
732 if (IS_ERR(bank->clk)) { in rockchip_gpio_probe()
733 bank->clk = of_clk_get(dev->of_node, 0); in rockchip_gpio_probe()
734 if (IS_ERR(bank->clk)) { in rockchip_gpio_probe()
736 return PTR_ERR(bank->clk); in rockchip_gpio_probe()
740 bank->db_clk = devm_clk_get(dev, "db"); in rockchip_gpio_probe()
741 if (IS_ERR(bank->db_clk)) { in rockchip_gpio_probe()
742 bank->db_clk = of_clk_get(dev->of_node, 1); in rockchip_gpio_probe()
743 if (IS_ERR(bank->db_clk)) in rockchip_gpio_probe()
744 bank->db_clk = NULL; in rockchip_gpio_probe()
748 clk_prepare_enable(bank->clk); in rockchip_gpio_probe()
749 clk_prepare_enable(bank->db_clk); in rockchip_gpio_probe()
751 rockchip_gpio_get_ver(bank); in rockchip_gpio_probe()
757 mutex_lock(&bank->deferred_lock); in rockchip_gpio_probe()
759 ret = rockchip_gpiolib_register(bank); in rockchip_gpio_probe()
761 dev_err(bank->dev, "Failed to register gpio %d\n", ret); in rockchip_gpio_probe()
765 if (!device_property_read_bool(bank->dev, "gpio-ranges") && pctldev) { in rockchip_gpio_probe()
766 struct gpio_chip *gc = &bank->gpio_chip; in rockchip_gpio_probe()
771 dev_err(bank->dev, "Failed to add pin range\n"); in rockchip_gpio_probe()
776 while (!list_empty(&bank->deferred_pins)) { in rockchip_gpio_probe()
779 cfg = list_first_entry(&bank->deferred_pins, in rockchip_gpio_probe()
788 ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg); in rockchip_gpio_probe()
800 mutex_unlock(&bank->deferred_lock); in rockchip_gpio_probe()
802 platform_set_drvdata(pdev, bank); in rockchip_gpio_probe()
807 mutex_unlock(&bank->deferred_lock); in rockchip_gpio_probe()
808 clk_disable_unprepare(bank->clk); in rockchip_gpio_probe()
809 clk_disable_unprepare(bank->db_clk); in rockchip_gpio_probe()
816 struct rockchip_pin_bank *bank = platform_get_drvdata(pdev); in rockchip_gpio_remove() local
818 clk_disable_unprepare(bank->clk); in rockchip_gpio_remove()
819 clk_disable_unprepare(bank->db_clk); in rockchip_gpio_remove()
820 gpiochip_remove(&bank->gpio_chip); in rockchip_gpio_remove()
826 { .compatible = "rockchip,gpio-bank", },