Lines Matching refs:pl061
50 struct pl061 { struct
65 struct pl061 *pl061 = gpiochip_get_data(gc); in pl061_get_direction() argument
67 if (readb(pl061->base + GPIODIR) & BIT(offset)) in pl061_get_direction()
75 struct pl061 *pl061 = gpiochip_get_data(gc); in pl061_direction_input() local
79 raw_spin_lock_irqsave(&pl061->lock, flags); in pl061_direction_input()
80 gpiodir = readb(pl061->base + GPIODIR); in pl061_direction_input()
82 writeb(gpiodir, pl061->base + GPIODIR); in pl061_direction_input()
83 raw_spin_unlock_irqrestore(&pl061->lock, flags); in pl061_direction_input()
91 struct pl061 *pl061 = gpiochip_get_data(gc); in pl061_direction_output() local
95 raw_spin_lock_irqsave(&pl061->lock, flags); in pl061_direction_output()
96 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); in pl061_direction_output()
97 gpiodir = readb(pl061->base + GPIODIR); in pl061_direction_output()
99 writeb(gpiodir, pl061->base + GPIODIR); in pl061_direction_output()
105 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); in pl061_direction_output()
106 raw_spin_unlock_irqrestore(&pl061->lock, flags); in pl061_direction_output()
113 struct pl061 *pl061 = gpiochip_get_data(gc); in pl061_get_value() local
115 return !!readb(pl061->base + (BIT(offset + 2))); in pl061_get_value()
120 struct pl061 *pl061 = gpiochip_get_data(gc); in pl061_set_value() local
122 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); in pl061_set_value()
128 struct pl061 *pl061 = gpiochip_get_data(gc); in pl061_irq_type() local
148 raw_spin_lock_irqsave(&pl061->lock, flags); in pl061_irq_type()
150 gpioiev = readb(pl061->base + GPIOIEV); in pl061_irq_type()
151 gpiois = readb(pl061->base + GPIOIS); in pl061_irq_type()
152 gpioibe = readb(pl061->base + GPIOIBE); in pl061_irq_type()
204 writeb(gpiois, pl061->base + GPIOIS); in pl061_irq_type()
205 writeb(gpioibe, pl061->base + GPIOIBE); in pl061_irq_type()
206 writeb(gpioiev, pl061->base + GPIOIEV); in pl061_irq_type()
208 raw_spin_unlock_irqrestore(&pl061->lock, flags); in pl061_irq_type()
218 struct pl061 *pl061 = gpiochip_get_data(gc); in pl061_irq_handler() local
223 pending = readb(pl061->base + GPIOMIS); in pl061_irq_handler()
236 struct pl061 *pl061 = gpiochip_get_data(gc); in pl061_irq_mask() local
240 raw_spin_lock(&pl061->lock); in pl061_irq_mask()
241 gpioie = readb(pl061->base + GPIOIE) & ~mask; in pl061_irq_mask()
242 writeb(gpioie, pl061->base + GPIOIE); in pl061_irq_mask()
243 raw_spin_unlock(&pl061->lock); in pl061_irq_mask()
249 struct pl061 *pl061 = gpiochip_get_data(gc); in pl061_irq_unmask() local
253 raw_spin_lock(&pl061->lock); in pl061_irq_unmask()
254 gpioie = readb(pl061->base + GPIOIE) | mask; in pl061_irq_unmask()
255 writeb(gpioie, pl061->base + GPIOIE); in pl061_irq_unmask()
256 raw_spin_unlock(&pl061->lock); in pl061_irq_unmask()
270 struct pl061 *pl061 = gpiochip_get_data(gc); in pl061_irq_ack() local
273 raw_spin_lock(&pl061->lock); in pl061_irq_ack()
274 writeb(mask, pl061->base + GPIOIC); in pl061_irq_ack()
275 raw_spin_unlock(&pl061->lock); in pl061_irq_ack()
281 struct pl061 *pl061 = gpiochip_get_data(gc); in pl061_irq_set_wake() local
283 return irq_set_irq_wake(pl061->parent_irq, state); in pl061_irq_set_wake()
289 struct pl061 *pl061; in pl061_probe() local
293 pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL); in pl061_probe()
294 if (pl061 == NULL) in pl061_probe()
297 pl061->base = devm_ioremap_resource(dev, &adev->res); in pl061_probe()
298 if (IS_ERR(pl061->base)) in pl061_probe()
299 return PTR_ERR(pl061->base); in pl061_probe()
301 raw_spin_lock_init(&pl061->lock); in pl061_probe()
302 pl061->gc.request = gpiochip_generic_request; in pl061_probe()
303 pl061->gc.free = gpiochip_generic_free; in pl061_probe()
304 pl061->gc.base = -1; in pl061_probe()
305 pl061->gc.get_direction = pl061_get_direction; in pl061_probe()
306 pl061->gc.direction_input = pl061_direction_input; in pl061_probe()
307 pl061->gc.direction_output = pl061_direction_output; in pl061_probe()
308 pl061->gc.get = pl061_get_value; in pl061_probe()
309 pl061->gc.set = pl061_set_value; in pl061_probe()
310 pl061->gc.ngpio = PL061_GPIO_NR; in pl061_probe()
311 pl061->gc.label = dev_name(dev); in pl061_probe()
312 pl061->gc.parent = dev; in pl061_probe()
313 pl061->gc.owner = THIS_MODULE; in pl061_probe()
318 pl061->irq_chip.name = dev_name(dev); in pl061_probe()
319 pl061->irq_chip.irq_ack = pl061_irq_ack; in pl061_probe()
320 pl061->irq_chip.irq_mask = pl061_irq_mask; in pl061_probe()
321 pl061->irq_chip.irq_unmask = pl061_irq_unmask; in pl061_probe()
322 pl061->irq_chip.irq_set_type = pl061_irq_type; in pl061_probe()
323 pl061->irq_chip.irq_set_wake = pl061_irq_set_wake; in pl061_probe()
325 writeb(0, pl061->base + GPIOIE); /* disable irqs */ in pl061_probe()
329 pl061->parent_irq = irq; in pl061_probe()
331 girq = &pl061->gc.irq; in pl061_probe()
332 girq->chip = &pl061->irq_chip; in pl061_probe()
343 ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061); in pl061_probe()
347 amba_set_drvdata(adev, pl061); in pl061_probe()
356 struct pl061 *pl061 = dev_get_drvdata(dev); in pl061_suspend() local
359 pl061->csave_regs.gpio_data = 0; in pl061_suspend()
360 pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR); in pl061_suspend()
361 pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS); in pl061_suspend()
362 pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE); in pl061_suspend()
363 pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV); in pl061_suspend()
364 pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE); in pl061_suspend()
367 if (pl061->csave_regs.gpio_dir & (BIT(offset))) in pl061_suspend()
368 pl061->csave_regs.gpio_data |= in pl061_suspend()
369 pl061_get_value(&pl061->gc, offset) << offset; in pl061_suspend()
377 struct pl061 *pl061 = dev_get_drvdata(dev); in pl061_resume() local
381 if (pl061->csave_regs.gpio_dir & (BIT(offset))) in pl061_resume()
382 pl061_direction_output(&pl061->gc, offset, in pl061_resume()
383 pl061->csave_regs.gpio_data & in pl061_resume()
386 pl061_direction_input(&pl061->gc, offset); in pl061_resume()
389 writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS); in pl061_resume()
390 writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE); in pl061_resume()
391 writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV); in pl061_resume()
392 writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE); in pl061_resume()