Lines Matching +full:big +full:- +full:endian +full:- +full:regs
40 void __iomem *regs; member
51 * This hardware has a big endian bit assignment such that GPIO line 0 is
57 return BIT(31 - offset); in mpc_pin2mask()
71 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); in mpc8572_gpio_get()
72 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; in mpc8572_gpio_get()
73 out_shadow = gc->bgpio_data & out_mask; in mpc8572_gpio_get()
84 return -EINVAL; in mpc5121_gpio_dir_out()
86 return mpc8xxx_gc->direction_output(gc, gpio, val); in mpc5121_gpio_dir_out()
95 return -EINVAL; in mpc5125_gpio_dir_out()
97 return mpc8xxx_gc->direction_output(gc, gpio, val); in mpc5125_gpio_dir_out()
104 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) in mpc8xxx_gpio_to_irq()
105 return irq_create_mapping(mpc8xxx_gc->irq, offset); in mpc8xxx_gpio_to_irq()
107 return -ENXIO; in mpc8xxx_gpio_to_irq()
113 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_gpio_irq_cascade()
117 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) in mpc8xxx_gpio_irq_cascade()
118 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); in mpc8xxx_gpio_irq_cascade()
120 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 31 - i)); in mpc8xxx_gpio_irq_cascade()
128 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_unmask()
131 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_unmask()
133 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, in mpc8xxx_irq_unmask()
134 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) in mpc8xxx_irq_unmask()
137 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_unmask()
143 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_mask()
146 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_mask()
148 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, in mpc8xxx_irq_mask()
149 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) in mpc8xxx_irq_mask()
152 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_mask()
158 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_ack()
160 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, in mpc8xxx_irq_ack()
167 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_set_type()
173 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
174 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, in mpc8xxx_irq_set_type()
175 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) in mpc8xxx_irq_set_type()
177 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
181 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
182 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, in mpc8xxx_irq_set_type()
183 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) in mpc8xxx_irq_set_type()
185 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
189 return -EINVAL; in mpc8xxx_irq_set_type()
198 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc512x_irq_set_type()
205 reg = mpc8xxx_gc->regs + GPIO_ICR; in mpc512x_irq_set_type()
206 shift = (15 - gpio) * 2; in mpc512x_irq_set_type()
208 reg = mpc8xxx_gc->regs + GPIO_ICR2; in mpc512x_irq_set_type()
209 shift = (15 - (gpio % 16)) * 2; in mpc512x_irq_set_type()
215 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
216 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) in mpc512x_irq_set_type()
218 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
223 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
224 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) in mpc512x_irq_set_type()
226 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
230 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
231 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))); in mpc512x_irq_set_type()
232 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
236 return -EINVAL; in mpc512x_irq_set_type()
243 .name = "mpc8xxx-gpio",
254 irq_set_chip_data(irq, h->host_data); in mpc8xxx_gpio_irq_map()
290 { .compatible = "fsl,mpc8349-gpio", },
291 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
292 { .compatible = "fsl,mpc8610-gpio", },
293 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
294 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
295 { .compatible = "fsl,pq3-gpio", },
296 { .compatible = "fsl,ls1028a-gpio", },
297 { .compatible = "fsl,ls1088a-gpio", },
298 { .compatible = "fsl,qoriq-gpio", },
304 struct device_node *np = pdev->dev.of_node; in mpc8xxx_probe()
308 of_device_get_match_data(&pdev->dev); in mpc8xxx_probe()
311 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL); in mpc8xxx_probe()
313 return -ENOMEM; in mpc8xxx_probe()
317 raw_spin_lock_init(&mpc8xxx_gc->lock); in mpc8xxx_probe()
319 mpc8xxx_gc->regs = of_iomap(np, 0); in mpc8xxx_probe()
320 if (!mpc8xxx_gc->regs) in mpc8xxx_probe()
321 return -ENOMEM; in mpc8xxx_probe()
323 gc = &mpc8xxx_gc->gc; in mpc8xxx_probe()
324 gc->parent = &pdev->dev; in mpc8xxx_probe()
326 if (of_property_read_bool(np, "little-endian")) { in mpc8xxx_probe()
327 ret = bgpio_init(gc, &pdev->dev, 4, in mpc8xxx_probe()
328 mpc8xxx_gc->regs + GPIO_DAT, in mpc8xxx_probe()
330 mpc8xxx_gc->regs + GPIO_DIR, NULL, in mpc8xxx_probe()
334 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n"); in mpc8xxx_probe()
336 ret = bgpio_init(gc, &pdev->dev, 4, in mpc8xxx_probe()
337 mpc8xxx_gc->regs + GPIO_DAT, in mpc8xxx_probe()
339 mpc8xxx_gc->regs + GPIO_DIR, NULL, in mpc8xxx_probe()
344 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n"); in mpc8xxx_probe()
347 mpc8xxx_gc->direction_output = gc->direction_output; in mpc8xxx_probe()
356 if (devtype->irq_set_type) in mpc8xxx_probe()
357 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type; in mpc8xxx_probe()
359 if (devtype->gpio_dir_out) in mpc8xxx_probe()
360 gc->direction_output = devtype->gpio_dir_out; in mpc8xxx_probe()
361 if (devtype->gpio_get) in mpc8xxx_probe()
362 gc->get = devtype->gpio_get; in mpc8xxx_probe()
364 gc->to_irq = mpc8xxx_gpio_to_irq; in mpc8xxx_probe()
373 if (of_device_is_compatible(np, "fsl,qoriq-gpio") || in mpc8xxx_probe()
374 of_device_is_compatible(np, "fsl,ls1028a-gpio") || in mpc8xxx_probe()
375 of_device_is_compatible(np, "fsl,ls1088a-gpio")) in mpc8xxx_probe()
376 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); in mpc8xxx_probe()
378 ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc); in mpc8xxx_probe()
385 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0); in mpc8xxx_probe()
386 if (!mpc8xxx_gc->irqn) in mpc8xxx_probe()
389 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS, in mpc8xxx_probe()
391 if (!mpc8xxx_gc->irq) in mpc8xxx_probe()
395 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff); in mpc8xxx_probe()
396 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0); in mpc8xxx_probe()
398 ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn, in mpc8xxx_probe()
400 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade", in mpc8xxx_probe()
403 dev_err(&pdev->dev, "%s: failed to devm_request_irq(%d), ret = %d\n", in mpc8xxx_probe()
404 np->full_name, mpc8xxx_gc->irqn, ret); in mpc8xxx_probe()
410 if (mpc8xxx_gc->irq) in mpc8xxx_probe()
411 irq_domain_remove(mpc8xxx_gc->irq); in mpc8xxx_probe()
412 iounmap(mpc8xxx_gc->regs); in mpc8xxx_probe()
420 if (mpc8xxx_gc->irq) { in mpc8xxx_remove()
421 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL); in mpc8xxx_remove()
422 irq_domain_remove(mpc8xxx_gc->irq); in mpc8xxx_remove()
425 iounmap(mpc8xxx_gc->regs); in mpc8xxx_remove()
434 .name = "gpio-mpc8xxx",