97 } ichx_priv;  variable
110 	spin_lock_irqsave(&ichx_priv.lock, flags);  in ichx_write_bit()
112 	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)  in ichx_write_bit()
113 		data = ichx_priv.outlvl_cache[reg_nr];  in ichx_write_bit()
115 		data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],  in ichx_write_bit()
116 				 ichx_priv.gpio_base);  in ichx_write_bit()
122 	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],  in ichx_write_bit()
123 			 ichx_priv.gpio_base);  in ichx_write_bit()
124 	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)  in ichx_write_bit()
125 		ichx_priv.outlvl_cache[reg_nr] = data;  in ichx_write_bit()
127 	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],  in ichx_write_bit()
128 			ichx_priv.gpio_base);  in ichx_write_bit()
130 	spin_unlock_irqrestore(&ichx_priv.lock, flags);  in ichx_write_bit()
142 	spin_lock_irqsave(&ichx_priv.lock, flags);  in ichx_read_bit()
144 	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],  in ichx_read_bit()
145 			 ichx_priv.gpio_base);  in ichx_read_bit()
147 	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)  in ichx_read_bit()
148 		data = ichx_priv.outlvl_cache[reg_nr] | data;  in ichx_read_bit()
150 	spin_unlock_irqrestore(&ichx_priv.lock, flags);  in ichx_read_bit()
157 	return !!(ichx_priv.use_gpio & BIT(nr / 32));  in ichx_gpio_check_available()
181 	if (nr < 32 && ichx_priv.desc->have_blink)  in ichx_gpio_direction_output()
209 		if (!ichx_priv.pm_base)  in ich6_gpio_get()
212 		spin_lock_irqsave(&ichx_priv.lock, flags);  in ich6_gpio_get()
215 		ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base);  in ich6_gpio_get()
216 		data = ICHX_READ(0, ichx_priv.pm_base);  in ich6_gpio_get()
218 		spin_unlock_irqrestore(&ichx_priv.lock, flags);  in ich6_gpio_get()
237 	if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f))  in ichx_gpio_request()
266 	chip->parent = ichx_priv.dev;  in ichx_gpiolib_setup()
269 	chip->request = ichx_priv.desc->request ?  in ichx_gpiolib_setup()
270 		ichx_priv.desc->request : ichx_gpio_request;  in ichx_gpiolib_setup()
271 	chip->get = ichx_priv.desc->get ?  in ichx_gpiolib_setup()
272 		ichx_priv.desc->get : ichx_gpio_get;  in ichx_gpiolib_setup()
279 	chip->ngpio = ichx_priv.desc->ngpio;  in ichx_gpiolib_setup()
376 	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {  in ichx_gpio_request_regions()
380 				res_base->start + ichx_priv.desc->regs[0][i],  in ichx_gpio_request_regions()
381 				ichx_priv.desc->reglen[i], name))  in ichx_gpio_request_regions()
399 		ichx_priv.desc = &i3100_desc;  in ichx_gpio_probe()
402 		ichx_priv.desc = &intel5_desc;  in ichx_gpio_probe()
405 		ichx_priv.desc = &ich6_desc;  in ichx_gpio_probe()
408 		ichx_priv.desc = &ich7_desc;  in ichx_gpio_probe()
411 		ichx_priv.desc = &ich9_desc;  in ichx_gpio_probe()
414 		ichx_priv.desc = &ich10_corp_desc;  in ichx_gpio_probe()
417 		ichx_priv.desc = &ich10_cons_desc;  in ichx_gpio_probe()
420 		ichx_priv.desc = &avoton_desc;  in ichx_gpio_probe()
426 	ichx_priv.dev = dev;  in ichx_gpio_probe()
427 	spin_lock_init(&ichx_priv.lock);  in ichx_gpio_probe()
435 	ichx_priv.gpio_base = res_base;  in ichx_gpio_probe()
436 	ichx_priv.use_gpio = ich_info->use_gpio;  in ichx_gpio_probe()
443 	if (!ichx_priv.desc->uses_gpe0)  in ichx_gpio_probe()
458 	ichx_priv.pm_base = res_pm;  in ichx_gpio_probe()
461 	ichx_gpiolib_setup(&ichx_priv.chip);  in ichx_gpio_probe()
462 	err = gpiochip_add_data(&ichx_priv.chip, NULL);  in ichx_gpio_probe()
468 	dev_info(dev, "GPIO from %d to %d\n", ichx_priv.chip.base,  in ichx_gpio_probe()
469 		 ichx_priv.chip.base + ichx_priv.chip.ngpio - 1);  in ichx_gpio_probe()
476 	gpiochip_remove(&ichx_priv.chip);  in ichx_gpio_remove()