60 	struct hlwd_gpio *hlwd =  in hlwd_gpio_irqhandler()  local
68 	spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irqhandler()
69 	pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);  in hlwd_gpio_irqhandler()
70 	pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);  in hlwd_gpio_irqhandler()
73 	emulated_pending = hlwd->edge_emulation & pending;  in hlwd_gpio_irqhandler()
78 		level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);  in hlwd_gpio_irqhandler()
84 			    hlwd->regs + HW_GPIOB_INTLVL);  in hlwd_gpio_irqhandler()
87 		iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);  in hlwd_gpio_irqhandler()
90 		rising &= hlwd->rising_edge;  in hlwd_gpio_irqhandler()
91 		falling &= hlwd->falling_edge;  in hlwd_gpio_irqhandler()
96 	spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irqhandler()
101 		int irq = irq_find_mapping(hlwd->gpioc.irq.domain, hwirq);  in hlwd_gpio_irqhandler()
111 	struct hlwd_gpio *hlwd =  in hlwd_gpio_irq_ack()  local
114 	iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG);  in hlwd_gpio_irq_ack()
119 	struct hlwd_gpio *hlwd =  in hlwd_gpio_irq_mask()  local
124 	spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irq_mask()
125 	mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);  in hlwd_gpio_irq_mask()
127 	iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);  in hlwd_gpio_irq_mask()
128 	spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irq_mask()
133 	struct hlwd_gpio *hlwd =  in hlwd_gpio_irq_unmask()  local
138 	spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irq_unmask()
139 	mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);  in hlwd_gpio_irq_unmask()
141 	iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);  in hlwd_gpio_irq_unmask()
142 	spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irq_unmask()
151 static void hlwd_gpio_irq_setup_emulation(struct hlwd_gpio *hlwd, int hwirq,  in hlwd_gpio_irq_setup_emulation()  argument
157 	level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);  in hlwd_gpio_irq_setup_emulation()
158 	state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq);  in hlwd_gpio_irq_setup_emulation()
161 	iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);  in hlwd_gpio_irq_setup_emulation()
163 	hlwd->edge_emulation |= BIT(hwirq);  in hlwd_gpio_irq_setup_emulation()
164 	hlwd->rising_edge &= ~BIT(hwirq);  in hlwd_gpio_irq_setup_emulation()
165 	hlwd->falling_edge &= ~BIT(hwirq);  in hlwd_gpio_irq_setup_emulation()
167 		hlwd->rising_edge |= BIT(hwirq);  in hlwd_gpio_irq_setup_emulation()
169 		hlwd->falling_edge |= BIT(hwirq);  in hlwd_gpio_irq_setup_emulation()
174 	struct hlwd_gpio *hlwd =  in hlwd_gpio_irq_set_type()  local
179 	spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irq_set_type()
181 	hlwd->edge_emulation &= ~BIT(data->hwirq);  in hlwd_gpio_irq_set_type()
185 		level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);  in hlwd_gpio_irq_set_type()
187 		iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);  in hlwd_gpio_irq_set_type()
190 		level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);  in hlwd_gpio_irq_set_type()
192 		iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);  in hlwd_gpio_irq_set_type()
197 		hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type);  in hlwd_gpio_irq_set_type()
200 		spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irq_set_type()
204 	spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);  in hlwd_gpio_irq_set_type()
210 	struct hlwd_gpio *hlwd;  in hlwd_gpio_probe()  local
214 	hlwd = devm_kzalloc(&pdev->dev, sizeof(*hlwd), GFP_KERNEL);  in hlwd_gpio_probe()
215 	if (!hlwd)  in hlwd_gpio_probe()
218 	hlwd->regs = devm_platform_ioremap_resource(pdev, 0);  in hlwd_gpio_probe()
219 	if (IS_ERR(hlwd->regs))  in hlwd_gpio_probe()
220 		return PTR_ERR(hlwd->regs);  in hlwd_gpio_probe()
231 	iowrite32be(0xffffffff, hlwd->regs + HW_GPIO_OWNER);  in hlwd_gpio_probe()
233 	res = bgpio_init(&hlwd->gpioc, &pdev->dev, 4,  in hlwd_gpio_probe()
234 			hlwd->regs + HW_GPIOB_IN, hlwd->regs + HW_GPIOB_OUT,  in hlwd_gpio_probe()
235 			NULL, hlwd->regs + HW_GPIOB_DIR, NULL,  in hlwd_gpio_probe()
245 	hlwd->gpioc.ngpio = ngpios;  in hlwd_gpio_probe()
248 	iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK);  in hlwd_gpio_probe()
249 	iowrite32be(0xffffffff, hlwd->regs + HW_GPIOB_INTFLAG);  in hlwd_gpio_probe()
258 		hlwd->irq = platform_get_irq(pdev, 0);  in hlwd_gpio_probe()
259 		if (hlwd->irq < 0) {  in hlwd_gpio_probe()
261 				 hlwd->irq);  in hlwd_gpio_probe()
262 			return hlwd->irq;  in hlwd_gpio_probe()
265 		hlwd->irqc.name = dev_name(&pdev->dev);  in hlwd_gpio_probe()
266 		hlwd->irqc.irq_mask = hlwd_gpio_irq_mask;  in hlwd_gpio_probe()
267 		hlwd->irqc.irq_unmask = hlwd_gpio_irq_unmask;  in hlwd_gpio_probe()
268 		hlwd->irqc.irq_enable = hlwd_gpio_irq_enable;  in hlwd_gpio_probe()
269 		hlwd->irqc.irq_set_type = hlwd_gpio_irq_set_type;  in hlwd_gpio_probe()
271 		girq = &hlwd->gpioc.irq;  in hlwd_gpio_probe()
272 		girq->chip = &hlwd->irqc;  in hlwd_gpio_probe()
280 		girq->parents[0] = hlwd->irq;  in hlwd_gpio_probe()
285 	return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);  in hlwd_gpio_probe()