49 	struct gpio_chip gc;  member
74 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)  in brcmstb_gpio_gc_to_priv()  argument
76 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);  in brcmstb_gpio_gc_to_priv()
85 	return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &  in __brcmstb_gpio_get_active_irqs()
86 	       bank->gc.read_reg(reg_base + GIO_MASK(bank->id));  in __brcmstb_gpio_get_active_irqs()
95 	spin_lock_irqsave(&bank->gc.bgpio_lock, flags);  in brcmstb_gpio_get_active_irqs()
97 	spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);  in brcmstb_gpio_get_active_irqs()
105 	return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);  in brcmstb_gpio_hwirq_to_offset()
111 	struct gpio_chip *gc = &bank->gc;  in brcmstb_gpio_set_imask()  local
117 	spin_lock_irqsave(&gc->bgpio_lock, flags);  in brcmstb_gpio_set_imask()
118 	imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));  in brcmstb_gpio_set_imask()
123 	gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);  in brcmstb_gpio_set_imask()
124 	spin_unlock_irqrestore(&gc->bgpio_lock, flags);  in brcmstb_gpio_set_imask()
127 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)  in brcmstb_gpio_to_irq()  argument
129 	struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);  in brcmstb_gpio_to_irq()
131 	int hwirq = offset + (gc->base - priv->gpio_base);  in brcmstb_gpio_to_irq()
142 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);  in brcmstb_gpio_irq_mask()  local
143 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);  in brcmstb_gpio_irq_mask()
150 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);  in brcmstb_gpio_irq_unmask()  local
151 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);  in brcmstb_gpio_irq_unmask()
158 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);  in brcmstb_gpio_irq_ack()  local
159 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);  in brcmstb_gpio_irq_ack()
163 	gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);  in brcmstb_gpio_irq_ack()
168 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);  in brcmstb_gpio_irq_set_type()  local
169 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);  in brcmstb_gpio_irq_set_type()
207 	spin_lock_irqsave(&bank->gc.bgpio_lock, flags);  in brcmstb_gpio_irq_set_type()
209 	iedge_config = bank->gc.read_reg(priv->reg_base +  in brcmstb_gpio_irq_set_type()
211 	iedge_insensitive = bank->gc.read_reg(priv->reg_base +  in brcmstb_gpio_irq_set_type()
213 	ilevel = bank->gc.read_reg(priv->reg_base +  in brcmstb_gpio_irq_set_type()
216 	bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),  in brcmstb_gpio_irq_set_type()
218 	bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),  in brcmstb_gpio_irq_set_type()
220 	bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),  in brcmstb_gpio_irq_set_type()
223 	spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);  in brcmstb_gpio_irq_set_type()
244 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);  in brcmstb_gpio_irq_set_wake()  local
245 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);  in brcmstb_gpio_irq_set_wake()
276 	int hwbase = bank->gc.base - priv->gpio_base;  in brcmstb_gpio_irq_bank_handler()
317 		i += bank->gc.ngpio;  in brcmstb_gpio_hwirq_to_bank()
346 	ret = irq_set_chip_data(irq, &bank->gc);  in brcmstb_gpio_irq_map()
413 		gpiochip_remove(&bank->gc);  in brcmstb_gpio_remove()
418 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,  in brcmstb_gpio_of_xlate()  argument
421 	struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);  in brcmstb_gpio_of_xlate()
422 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);  in brcmstb_gpio_of_xlate()
425 	if (gc->of_gpio_n_cells != 2) {  in brcmstb_gpio_of_xlate()
430 	if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))  in brcmstb_gpio_of_xlate()
433 	offset = gpiospec->args[0] - (gc->base - priv->gpio_base);  in brcmstb_gpio_of_xlate()
434 	if (offset >= gc->ngpio || offset < 0)  in brcmstb_gpio_of_xlate()
516 	struct gpio_chip *gc = &bank->gc;  in brcmstb_gpio_bank_save()  local
520 		bank->saved_regs[i] = gc->read_reg(priv->reg_base +  in brcmstb_gpio_bank_save()
528 	struct gpio_chip *gc;  in brcmstb_gpio_quiesce()  local
536 		gc = &bank->gc;  in brcmstb_gpio_quiesce()
546 		gc->write_reg(priv->reg_base + GIO_MASK(bank->id),  in brcmstb_gpio_quiesce()
561 	struct gpio_chip *gc = &bank->gc;  in brcmstb_gpio_bank_restore()  local
565 		gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),  in brcmstb_gpio_bank_restore()
646 	bank->gc.names = names;  in brcmstb_gpio_set_names()
706 		struct gpio_chip *gc;  in brcmstb_gpio_probe()  local
740 		gc = &bank->gc;  in brcmstb_gpio_probe()
741 		err = bgpio_init(gc, dev, 4,  in brcmstb_gpio_probe()
750 		gc->of_node = np;  in brcmstb_gpio_probe()
751 		gc->owner = THIS_MODULE;  in brcmstb_gpio_probe()
752 		gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", dev->of_node);  in brcmstb_gpio_probe()
753 		if (!gc->label) {  in brcmstb_gpio_probe()
757 		gc->base = gpio_base;  in brcmstb_gpio_probe()
758 		gc->of_gpio_n_cells = 2;  in brcmstb_gpio_probe()
759 		gc->of_xlate = brcmstb_gpio_of_xlate;  in brcmstb_gpio_probe()
761 		gc->ngpio = MAX_GPIO_PER_BANK;  in brcmstb_gpio_probe()
763 			gc->to_irq = brcmstb_gpio_to_irq;  in brcmstb_gpio_probe()
770 		gc->write_reg(reg_base + GIO_MASK(bank->id), 0);  in brcmstb_gpio_probe()
773 		err = gpiochip_add_data(gc, bank);  in brcmstb_gpio_probe()
779 		gpio_base += gc->ngpio;  in brcmstb_gpio_probe()
782 			gc->base, gc->ngpio, bank->width);  in brcmstb_gpio_probe()