Lines Matching refs:bank_reg
99 static void __iomem *bank_reg(struct aspeed_sgpio *gpio, in bank_reg() function
187 rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset)); in aspeed_sgpio_get()
206 addr_r = bank_reg(gpio, bank, reg_rdata); in sgpio_set_value()
207 addr_w = bank_reg(gpio, bank, reg_val); in sgpio_set_value()
286 status_addr = bank_reg(gpio, bank, reg_irq_status); in aspeed_sgpio_irq_ack()
305 addr = bank_reg(gpio, bank, reg_irq_enable); in aspeed_sgpio_irq_set_mask()
368 addr = bank_reg(gpio, bank, reg_irq_type0); in aspeed_sgpio_set_type()
373 addr = bank_reg(gpio, bank, reg_irq_type1); in aspeed_sgpio_set_type()
378 addr = bank_reg(gpio, bank, reg_irq_type2); in aspeed_sgpio_set_type()
403 reg = ioread32(bank_reg(data, bank, reg_irq_status)); in aspeed_sgpio_irq_handler()
440 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable)); in aspeed_sgpio_setup_irqs()
442 iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status)); in aspeed_sgpio_setup_irqs()
459 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0)); in aspeed_sgpio_setup_irqs()
461 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1)); in aspeed_sgpio_setup_irqs()
463 iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2)); in aspeed_sgpio_setup_irqs()