114 		edac_dbg(0, "In single channel mode\n");  in how_many_channels()
117 		edac_dbg(0, "In dual channel mode\n");  in how_many_channels()
122 		edac_dbg(0, "2 DIMMS per channel disabled\n");  in how_many_channels()
124 		edac_dbg(0, "2 DIMMS per channel enabled\n");  in how_many_channels()
256 	edac_dbg(1, "MC%d\n", mci->mc_idx);  in i3200_check()
301 		edac_dbg(0, "drb[0][%d] = %d, drb[1][%d] = %d\n", i, drbs[0][i], i, drbs[1][i]);  in i3200_get_drbs()
347 	edac_dbg(0, "MC:\n");  in i3200_probe1()
367 	edac_dbg(3, "MC: init mci\n");  in i3200_probe1()
401 			edac_dbg(0, "csrow %d, channel %d%s, size = %ld MiB\n", i, j,  in i3200_probe1()
416 		edac_dbg(3, "MC: failed edac_mc_add_mc()\n");  in i3200_probe1()
421 	edac_dbg(3, "MC: success\n");  in i3200_probe1()
436 	edac_dbg(0, "MC:\n");  in i3200_init_one()
453 	edac_dbg(0, "\n");  in i3200_remove_one()
489 	edac_dbg(3, "MC:\n");  in i3200_init()
503 			edac_dbg(0, "i3200 pci_get_device fail\n");  in i3200_init()
510 			edac_dbg(0, "i3200 init fail\n");  in i3200_init()
529 	edac_dbg(3, "MC:\n");  in i3200_exit()