217 	if (pvt->umc) {  in __set_scrub_rate()
259 	if (pvt->umc) {  in get_scrub_rate()
723 	if (pvt->umc) {  in determine_edac_cap()
727 			if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT))  in determine_edac_cap()
733 			if (pvt->umc[i].umc_cfg & BIT(12))  in determine_edac_cap()
849 	struct amd64_umc *umc;  in __dump_misc_regs_df()  local
854 		umc = &pvt->umc[i];  in __dump_misc_regs_df()
856 		edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);  in __dump_misc_regs_df()
857 		edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);  in __dump_misc_regs_df()
858 		edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);  in __dump_misc_regs_df()
859 		edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);  in __dump_misc_regs_df()
866 		edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);  in __dump_misc_regs_df()
869 				i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no",  in __dump_misc_regs_df()
870 				    (umc->umc_cap_hi & BIT(31)) ? "yes" : "no");  in __dump_misc_regs_df()
872 				i, (umc->umc_cfg & BIT(12)) ? "yes" : "no");  in __dump_misc_regs_df()
874 				i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no");  in __dump_misc_regs_df()
876 				i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no");  in __dump_misc_regs_df()
928 	if (pvt->umc)  in dump_misc_regs()
950 		int umc;  in prep_chip_selects()  local
952 		for_each_umc(umc) {  in prep_chip_selects()
953 			pvt->csels[umc].b_cnt = 4;  in prep_chip_selects()
954 			pvt->csels[umc].m_cnt = 2;  in prep_chip_selects()
971 	int cs, umc;  in read_umc_base_mask()  local
973 	for_each_umc(umc) {  in read_umc_base_mask()
974 		umc_base_reg = get_umc_base(umc) + UMCCH_BASE_ADDR;  in read_umc_base_mask()
975 		umc_base_reg_sec = get_umc_base(umc) + UMCCH_BASE_ADDR_SEC;  in read_umc_base_mask()
977 		for_each_chip_select(cs, umc, pvt) {  in read_umc_base_mask()
978 			base = &pvt->csels[umc].csbases[cs];  in read_umc_base_mask()
979 			base_sec = &pvt->csels[umc].csbases_sec[cs];  in read_umc_base_mask()
986 					 umc, cs, *base, base_reg);  in read_umc_base_mask()
990 					 umc, cs, *base_sec, base_reg_sec);  in read_umc_base_mask()
993 		umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK;  in read_umc_base_mask()
994 		umc_mask_reg_sec = get_umc_base(umc) + UMCCH_ADDR_MASK_SEC;  in read_umc_base_mask()
996 		for_each_chip_select_mask(cs, umc, pvt) {  in read_umc_base_mask()
997 			mask = &pvt->csels[umc].csmasks[cs];  in read_umc_base_mask()
998 			mask_sec = &pvt->csels[umc].csmasks_sec[cs];  in read_umc_base_mask()
1005 					 umc, cs, *mask, mask_reg);  in read_umc_base_mask()
1009 					 umc, cs, *mask_sec, mask_reg_sec);  in read_umc_base_mask()
1023 	if (pvt->umc)  in read_dct_base_mask()
1069 	if (pvt->umc) {  in determine_memory_type()
1070 		if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5))  in determine_memory_type()
1072 		else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4))  in determine_memory_type()
1459 		channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT);  in f17_early_channel_count()
1593 static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,  in f17_addr_mask_to_cs_size()  argument
1621 		addr_mask_orig = pvt->csels[umc].csmasks_sec[dimm];  in f17_addr_mask_to_cs_size()
1623 		addr_mask_orig = pvt->csels[umc].csmasks[dimm];  in f17_addr_mask_to_cs_size()
2693 	if (pvt->umc) {  in reserve_mc_sibling_devs()
2748 	if (pvt->umc) {  in free_mc_sibling_devs()
2761 	if (pvt->umc) {  in determine_ecc_sym_sz()
2766 			if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {  in determine_ecc_sym_sz()
2767 				if (pvt->umc[i].ecc_ctrl & BIT(9)) {  in determine_ecc_sym_sz()
2770 				} else if (pvt->umc[i].ecc_ctrl & BIT(7)) {  in determine_ecc_sym_sz()
2796 	struct amd64_umc *umc;  in __read_mc_regs_df()  local
2803 		umc = &pvt->umc[i];  in __read_mc_regs_df()
2805 		amd_smn_read(nid, umc_base + UMCCH_DIMM_CFG, &umc->dimm_cfg);  in __read_mc_regs_df()
2806 		amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg);  in __read_mc_regs_df()
2807 		amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl);  in __read_mc_regs_df()
2808 		amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl);  in __read_mc_regs_df()
2809 		amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi);  in __read_mc_regs_df()
2838 	if (pvt->umc) {  in read_mc_regs()
2934 	if (!pvt->umc) {  in get_csrow_nr_pages()
2958 	u8 umc, cs;  in init_csrows_df()  local
2973 	for_each_umc(umc) {  in init_csrows_df()
2974 		for_each_chip_select(cs, umc, pvt) {  in init_csrows_df()
2975 			if (!csrow_enabled(cs, umc, pvt))  in init_csrows_df()
2979 			dimm = mci->csrows[cs]->channels[umc]->dimm;  in init_csrows_df()
2984 			dimm->nr_pages = get_csrow_nr_pages(pvt, umc, cs);  in init_csrows_df()
3009 	if (pvt->umc)  in init_csrows()
3241 		struct amd64_umc *umc;  in ecc_enabled()  local
3244 			umc = &pvt->umc[i];  in ecc_enabled()
3247 			if (!(umc->sdp_ctrl & UMC_SDP_INIT))  in ecc_enabled()
3252 			if (umc->umc_cap_hi & UMC_ECC_ENABLED)  in ecc_enabled()
3290 		if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {  in f17h_determine_edac_ctl_cap()
3291 			ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED);  in f17h_determine_edac_ctl_cap()
3292 			cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP);  in f17h_determine_edac_ctl_cap()
3294 			dev_x4  &= !!(pvt->umc[i].dimm_cfg & BIT(6));  in f17h_determine_edac_ctl_cap()
3295 			dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7));  in f17h_determine_edac_ctl_cap()
3322 	if (pvt->umc) {  in setup_mci_misc_attrs()
3460 		pvt->umc = kcalloc(fam_type->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL);  in hw_info_get()
3461 		if (!pvt->umc)  in hw_info_get()
3485 	kfree(pvt->umc);  in hw_info_put()