375 	edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n",  in find_mc_by_sys_addr()
474 			edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n",  in input_addr_to_csrow()
481 	edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n",  in input_addr_to_csrow()
510 		edac_dbg(1, "  revision %d for node %d does not support DHAR\n",  in amd64_get_dram_hole_info()
517 		edac_dbg(1, "  Dram Memory Hoisting is DISABLED on this system\n");  in amd64_get_dram_hole_info()
522 		edac_dbg(1, "  Dram Memory Hoisting is DISABLED on this node %d\n",  in amd64_get_dram_hole_info()
551 	edac_dbg(1, "  DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",  in amd64_get_dram_hole_info()
604 			edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n",  in sys_addr_to_dram_addr()
623 	edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n",  in sys_addr_to_dram_addr()
660 	edac_dbg(2, "  Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",  in dram_addr_to_input_addr()
678 	edac_dbg(2, "SysAddr 0x%lx translates to InputAddr 0x%lx\n",  in sys_addr_to_input_addr()
755 	edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);  in debug_dump_dramcfg_low()
764 		edac_dbg(1, " LRDIMM %dx rank multiply\n", (dcsm & 0x3));  in debug_dump_dramcfg_low()
767 	edac_dbg(1, "All DIMMs support ECC:%s\n",  in debug_dump_dramcfg_low()
771 	edac_dbg(1, "  PAR/ERR parity: %s\n",  in debug_dump_dramcfg_low()
775 		edac_dbg(1, "  DCT 128bit mode width: %s\n",  in debug_dump_dramcfg_low()
778 	edac_dbg(1, "  x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",  in debug_dump_dramcfg_low()
819 		edac_dbg(1, "3R interleaving in use.\n");  in f17_get_cs_mode()
856 		edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);  in __dump_misc_regs_df()
857 		edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);  in __dump_misc_regs_df()
858 		edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);  in __dump_misc_regs_df()
859 		edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);  in __dump_misc_regs_df()
862 		edac_dbg(1, "UMC%d ECC bad symbol: 0x%x\n", i, tmp);  in __dump_misc_regs_df()
865 		edac_dbg(1, "UMC%d UMC cap: 0x%x\n", i, tmp);  in __dump_misc_regs_df()
866 		edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);  in __dump_misc_regs_df()
868 		edac_dbg(1, "UMC%d ECC capable: %s, ChipKill ECC capable: %s\n",  in __dump_misc_regs_df()
871 		edac_dbg(1, "UMC%d All DIMMs support ECC: %s\n",  in __dump_misc_regs_df()
873 		edac_dbg(1, "UMC%d x4 DIMMs present: %s\n",  in __dump_misc_regs_df()
875 		edac_dbg(1, "UMC%d x16 DIMMs present: %s\n",  in __dump_misc_regs_df()
880 			edac_dbg(1, "UMC%d LRDIMM %dx rank multiply\n",  in __dump_misc_regs_df()
887 	edac_dbg(1, "F0x104 (DRAM Hole Address): 0x%08x, base: 0x%08x\n",  in __dump_misc_regs_df()
894 	edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);  in __dump_misc_regs()
896 	edac_dbg(1, "  NB two channel DRAM capable: %s\n",  in __dump_misc_regs()
899 	edac_dbg(1, "  ECC capable: %s, ChipKill ECC capable: %s\n",  in __dump_misc_regs()
905 	edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);  in __dump_misc_regs()
907 	edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n",  in __dump_misc_regs()
933 	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");  in dump_misc_regs()
985 				edac_dbg(0, "  DCSB%d[%d]=0x%08x reg: 0x%x\n",  in read_umc_base_mask()
989 				edac_dbg(0, "    DCSB_SEC%d[%d]=0x%08x reg: 0x%x\n",  in read_umc_base_mask()
1004 				edac_dbg(0, "  DCSM%d[%d]=0x%08x reg: 0x%x\n",  in read_umc_base_mask()
1008 				edac_dbg(0, "    DCSM_SEC%d[%d]=0x%08x reg: 0x%x\n",  in read_umc_base_mask()
1033 			edac_dbg(0, "  DCSB0[%d]=0x%08x reg: F2x%x\n",  in read_dct_base_mask()
1040 			edac_dbg(0, "  DCSB1[%d]=0x%08x reg: F2x%x\n",  in read_dct_base_mask()
1052 			edac_dbg(0, "    DCSM0[%d]=0x%08x reg: F2x%x\n",  in read_dct_base_mask()
1059 			edac_dbg(0, "    DCSM1[%d]=0x%08x reg: F2x%x\n",  in read_dct_base_mask()
1427 	edac_dbg(0, "Data width is not 128 bits - need more decoding\n");  in f1x_early_channel_count()
1643 	edac_dbg(1, "CS%d DIMM%d AddrMasks:\n", csrow_nr, dimm);  in f17_addr_mask_to_cs_size()
1644 	edac_dbg(1, "  Original AddrMask: 0x%x\n", addr_mask_orig);  in f17_addr_mask_to_cs_size()
1645 	edac_dbg(1, "  Deinterleaved AddrMask: 0x%x\n", addr_mask_deinterleaved);  in f17_addr_mask_to_cs_size()
1661 		edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",  in read_dram_ctl_register()
1664 		edac_dbg(0, "  DCTs operate in %s mode\n",  in read_dram_ctl_register()
1668 			edac_dbg(0, "  Address range split per DCT: %s\n",  in read_dram_ctl_register()
1671 		edac_dbg(0, "  data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n",  in read_dram_ctl_register()
1675 		edac_dbg(0, "  channel interleave: %s, "  in read_dram_ctl_register()
1853 	edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct);  in f1x_lookup_addr_in_dct()
1861 		edac_dbg(1, "    CSROW=%d CSBase=0x%llx CSMask=0x%llx\n",  in f1x_lookup_addr_in_dct()
1866 		edac_dbg(1, "    (InputAddr & ~CSMask)=0x%llx (CSBase & ~CSMask)=0x%llx\n",  in f1x_lookup_addr_in_dct()
1876 			edac_dbg(1, " MATCH csrow=%d\n", cs_found);  in f1x_lookup_addr_in_dct()
1931 	edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",  in f1x_match_to_this_node()
1988 	edac_dbg(1, "   Normalized DCT addr: 0x%llx\n", chan_addr);  in f1x_match_to_this_node()
2019 	edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",  in f15_m30h_match_to_this_node()
2100 	edac_dbg(1, "   Normalized DCT addr: 0x%llx\n", chan_addr);  in f15_m30h_match_to_this_node()
2204 	edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",  in debug_display_dimm_sizes()
2476 	edac_dbg(0, "syndrome(%x) not found\n", syndrome);  in decode_syndrome()
2712 		edac_dbg(1, "F0: %s\n", pci_name(pvt->F0));  in reserve_mc_sibling_devs()
2713 		edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));  in reserve_mc_sibling_devs()
2714 		edac_dbg(1, "F6: %s\n", pci_name(pvt->F6));  in reserve_mc_sibling_devs()
2739 	edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));  in reserve_mc_sibling_devs()
2740 	edac_dbg(1, "F2: %s\n", pci_name(pvt->F2));  in reserve_mc_sibling_devs()
2741 	edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));  in reserve_mc_sibling_devs()
2827 	edac_dbg(0, "  TOP_MEM:  0x%016llx\n", pvt->top_mem);  in read_mc_regs()
2833 		edac_dbg(0, "  TOP_MEM2: 0x%016llx\n", pvt->top_mem2);  in read_mc_regs()
2835 		edac_dbg(0, "  TOP_MEM2 disabled\n");  in read_mc_regs()
2859 		edac_dbg(1, "  DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",  in read_mc_regs()
2864 		edac_dbg(1, "   IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n",  in read_mc_regs()
2889 	edac_dbg(1, "  DIMM type: %s\n", edac_mem_types[pvt->dram_type]);  in read_mc_regs()
2944 	edac_dbg(0, "csrow: %d, channel: %d, DBAM idx: %d\n",  in get_csrow_nr_pages()
2946 	edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);  in get_csrow_nr_pages()
2981 			edac_dbg(1, "MC node: %d, csrow: %d\n",  in init_csrows_df()
3016 	edac_dbg(0, "node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",  in init_csrows()
3036 		edac_dbg(1, "MC node: %d, csrow: %d\n",  in init_csrows()
3052 		edac_dbg(1, "Total csrow%d pages: %u\n", i, nr_pages);  in init_csrows()
3102 		edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",  in nb_mce_bank_enabled_on_node()
3175 	edac_dbg(0, "1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",  in enable_ecc_error_reporting()
3200 	edac_dbg(0, "2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",  in enable_ecc_error_reporting()
3260 			edac_dbg(0, "Node %d: No enabled UMCs.\n", nid);  in ecc_enabled()
3271 			edac_dbg(0, "NB MCE bank disabled, set MSR 0x%08x[4] on node %d to enable.\n",  in ecc_enabled()
3531 		edac_dbg(1, "failed edac_mc_add_mc()\n");  in init_one_instance()