2025 	struct cppi5_tr_type1_t *tr_req = NULL;  in udma_prep_slave_sg_tr()  local
2048 	tr_req = d->hwdesc[0].tr_req_base;  in udma_prep_slave_sg_tr()
2062 		cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false,  in udma_prep_slave_sg_tr()
2064 		cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT);  in udma_prep_slave_sg_tr()
2066 		tr_req[tr_idx].addr = sg_addr;  in udma_prep_slave_sg_tr()
2067 		tr_req[tr_idx].icnt0 = tr0_cnt0;  in udma_prep_slave_sg_tr()
2068 		tr_req[tr_idx].icnt1 = tr0_cnt1;  in udma_prep_slave_sg_tr()
2069 		tr_req[tr_idx].dim1 = tr0_cnt0;  in udma_prep_slave_sg_tr()
2073 			cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1,  in udma_prep_slave_sg_tr()
2076 			cppi5_tr_csf_set(&tr_req[tr_idx].flags,  in udma_prep_slave_sg_tr()
2079 			tr_req[tr_idx].addr = sg_addr + tr0_cnt1 * tr0_cnt0;  in udma_prep_slave_sg_tr()
2080 			tr_req[tr_idx].icnt0 = tr1_cnt0;  in udma_prep_slave_sg_tr()
2081 			tr_req[tr_idx].icnt1 = 1;  in udma_prep_slave_sg_tr()
2082 			tr_req[tr_idx].dim1 = tr1_cnt0;  in udma_prep_slave_sg_tr()
2089 	cppi5_tr_csf_set(&tr_req[tr_idx - 1].flags,  in udma_prep_slave_sg_tr()
2397 	struct cppi5_tr_type1_t *tr_req;  in udma_prep_dma_cyclic_tr()  local
2417 	tr_req = d->hwdesc[0].tr_req_base;  in udma_prep_dma_cyclic_tr()
2422 		cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false,  in udma_prep_dma_cyclic_tr()
2425 		tr_req[tr_idx].addr = period_addr;  in udma_prep_dma_cyclic_tr()
2426 		tr_req[tr_idx].icnt0 = tr0_cnt0;  in udma_prep_dma_cyclic_tr()
2427 		tr_req[tr_idx].icnt1 = tr0_cnt1;  in udma_prep_dma_cyclic_tr()
2428 		tr_req[tr_idx].dim1 = tr0_cnt0;  in udma_prep_dma_cyclic_tr()
2431 			cppi5_tr_csf_set(&tr_req[tr_idx].flags,  in udma_prep_dma_cyclic_tr()
2435 			cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1,  in udma_prep_dma_cyclic_tr()
2439 			tr_req[tr_idx].addr = period_addr + tr0_cnt1 * tr0_cnt0;  in udma_prep_dma_cyclic_tr()
2440 			tr_req[tr_idx].icnt0 = tr1_cnt0;  in udma_prep_dma_cyclic_tr()
2441 			tr_req[tr_idx].icnt1 = 1;  in udma_prep_dma_cyclic_tr()
2442 			tr_req[tr_idx].dim1 = tr1_cnt0;  in udma_prep_dma_cyclic_tr()
2446 			cppi5_tr_csf_set(&tr_req[tr_idx].flags,  in udma_prep_dma_cyclic_tr()
2593 	struct cppi5_tr_type15_t *tr_req;  in udma_prep_dma_memcpy()  local
2624 	tr_req = d->hwdesc[0].tr_req_base;  in udma_prep_dma_memcpy()
2626 	cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true,  in udma_prep_dma_memcpy()
2628 	cppi5_tr_csf_set(&tr_req[0].flags, CPPI5_TR_CSF_SUPR_EVT);  in udma_prep_dma_memcpy()
2630 	tr_req[0].addr = src;  in udma_prep_dma_memcpy()
2631 	tr_req[0].icnt0 = tr0_cnt0;  in udma_prep_dma_memcpy()
2632 	tr_req[0].icnt1 = tr0_cnt1;  in udma_prep_dma_memcpy()
2633 	tr_req[0].icnt2 = 1;  in udma_prep_dma_memcpy()
2634 	tr_req[0].icnt3 = 1;  in udma_prep_dma_memcpy()
2635 	tr_req[0].dim1 = tr0_cnt0;  in udma_prep_dma_memcpy()
2637 	tr_req[0].daddr = dest;  in udma_prep_dma_memcpy()
2638 	tr_req[0].dicnt0 = tr0_cnt0;  in udma_prep_dma_memcpy()
2639 	tr_req[0].dicnt1 = tr0_cnt1;  in udma_prep_dma_memcpy()
2640 	tr_req[0].dicnt2 = 1;  in udma_prep_dma_memcpy()
2641 	tr_req[0].dicnt3 = 1;  in udma_prep_dma_memcpy()
2642 	tr_req[0].ddim1 = tr0_cnt0;  in udma_prep_dma_memcpy()
2645 		cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true,  in udma_prep_dma_memcpy()
2647 		cppi5_tr_csf_set(&tr_req[1].flags, CPPI5_TR_CSF_SUPR_EVT);  in udma_prep_dma_memcpy()
2649 		tr_req[1].addr = src + tr0_cnt1 * tr0_cnt0;  in udma_prep_dma_memcpy()
2650 		tr_req[1].icnt0 = tr1_cnt0;  in udma_prep_dma_memcpy()
2651 		tr_req[1].icnt1 = 1;  in udma_prep_dma_memcpy()
2652 		tr_req[1].icnt2 = 1;  in udma_prep_dma_memcpy()
2653 		tr_req[1].icnt3 = 1;  in udma_prep_dma_memcpy()
2655 		tr_req[1].daddr = dest + tr0_cnt1 * tr0_cnt0;  in udma_prep_dma_memcpy()
2656 		tr_req[1].dicnt0 = tr1_cnt0;  in udma_prep_dma_memcpy()
2657 		tr_req[1].dicnt1 = 1;  in udma_prep_dma_memcpy()
2658 		tr_req[1].dicnt2 = 1;  in udma_prep_dma_memcpy()
2659 		tr_req[1].dicnt3 = 1;  in udma_prep_dma_memcpy()
2662 	cppi5_tr_csf_set(&tr_req[num_tr - 1].flags,  in udma_prep_dma_memcpy()
3346 	struct cppi5_tr_type1_t *tr_req;  in udma_setup_rx_flush()  local
3393 	tr_req = hwdesc->tr_req_base;  in udma_setup_rx_flush()
3394 	cppi5_tr_init(&tr_req->flags, CPPI5_TR_TYPE1, false, false,  in udma_setup_rx_flush()
3396 	cppi5_tr_csf_set(&tr_req->flags, CPPI5_TR_CSF_SUPR_EVT);  in udma_setup_rx_flush()
3398 	tr_req->addr = rx_flush->buffer_paddr;  in udma_setup_rx_flush()
3399 	tr_req->icnt0 = rx_flush->buffer_size;  in udma_setup_rx_flush()
3400 	tr_req->icnt1 = 1;  in udma_setup_rx_flush()