Lines Matching refs:stm32_dma_write
245 static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val) in stm32_dma_write() function
428 stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr); in stm32_dma_irq_clear()
430 stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr); in stm32_dma_irq_clear()
444 stm32_dma_write(dmadev, reg, dma_scr); in stm32_dma_disable_chan()
463 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); in stm32_dma_stop()
466 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr); in stm32_dma_stop()
564 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); in stm32_dma_start_transfer()
565 stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar); in stm32_dma_start_transfer()
566 stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar); in stm32_dma_start_transfer()
567 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr); in stm32_dma_start_transfer()
568 stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar); in stm32_dma_start_transfer()
569 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr); in stm32_dma_start_transfer()
585 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); in stm32_dma_start_transfer()
609 stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar); in stm32_dma_configure_next_sg()
614 stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar); in stm32_dma_configure_next_sg()