Lines Matching refs:DMA_CCR
69 #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ macro
321 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) | in imxdma_enable_hw()
322 CCR_CEN | CCR_ACRPT, DMA_CCR(channel)); in imxdma_enable_hw()
330 tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel)); in imxdma_enable_hw()
332 DMA_CCR(channel)); in imxdma_enable_hw()
353 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) & in imxdma_disable_hw()
354 ~CCR_CEN, DMA_CCR(channel)); in imxdma_disable_hw()
365 imx_dmav1_writel(imxdma, 0, DMA_CCR(channel)); in imxdma_watchdog()
451 tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno)); in dma_irq_handle_channel()
461 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); in dma_irq_handle_channel()
464 DMA_CCR(chno)); in dma_irq_handle_channel()
468 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); in dma_irq_handle_channel()
484 imx_dmav1_writel(imxdma, 0, DMA_CCR(chno)); in dma_irq_handle_channel()
563 DMA_CCR(imxdmac->channel)); in imxdma_xfer_desc()
581 DMA_CCR(imxdmac->channel)); in imxdma_xfer_desc()
592 DMA_CCR(imxdmac->channel)); in imxdma_xfer_desc()