Lines Matching refs:fsl_edma
32 struct fsl_edma_engine *fsl_edma = dev_id; in fsl_edma_tx_handler() local
34 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_tx_handler()
37 intr = edma_readl(fsl_edma, regs->intl); in fsl_edma_tx_handler()
41 for (ch = 0; ch < fsl_edma->n_chans; ch++) { in fsl_edma_tx_handler()
43 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); in fsl_edma_tx_handler()
45 fsl_chan = &fsl_edma->chans[ch]; in fsl_edma_tx_handler()
76 struct fsl_edma_engine *fsl_edma = dev_id; in fsl_edma_err_handler() local
78 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_err_handler()
80 err = edma_readl(fsl_edma, regs->errl); in fsl_edma_err_handler()
84 for (ch = 0; ch < fsl_edma->n_chans; ch++) { in fsl_edma_err_handler()
86 fsl_edma_disable_request(&fsl_edma->chans[ch]); in fsl_edma_err_handler()
87 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); in fsl_edma_err_handler()
88 fsl_edma->chans[ch].status = DMA_ERROR; in fsl_edma_err_handler()
89 fsl_edma->chans[ch].idle = true; in fsl_edma_err_handler()
106 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; in fsl_edma_xlate() local
109 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs; in fsl_edma_xlate()
110 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr; in fsl_edma_xlate()
115 mutex_lock(&fsl_edma->fsl_edma_mutex); in fsl_edma_xlate()
116 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { in fsl_edma_xlate()
127 mutex_unlock(&fsl_edma->fsl_edma_mutex); in fsl_edma_xlate()
132 mutex_unlock(&fsl_edma->fsl_edma_mutex); in fsl_edma_xlate()
137 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) in fsl_edma_irq_init() argument
141 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); in fsl_edma_irq_init()
142 if (fsl_edma->txirq < 0) in fsl_edma_irq_init()
143 return fsl_edma->txirq; in fsl_edma_irq_init()
145 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); in fsl_edma_irq_init()
146 if (fsl_edma->errirq < 0) in fsl_edma_irq_init()
147 return fsl_edma->errirq; in fsl_edma_irq_init()
149 if (fsl_edma->txirq == fsl_edma->errirq) { in fsl_edma_irq_init()
150 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, in fsl_edma_irq_init()
151 fsl_edma_irq_handler, 0, "eDMA", fsl_edma); in fsl_edma_irq_init()
157 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, in fsl_edma_irq_init()
158 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma); in fsl_edma_irq_init()
164 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, in fsl_edma_irq_init()
165 fsl_edma_err_handler, 0, "eDMA err", fsl_edma); in fsl_edma_irq_init()
177 struct fsl_edma_engine *fsl_edma) in fsl_edma2_irq_init() argument
199 sprintf(fsl_edma->chans[i].chan_name, "eDMA2-CH%02d", i); in fsl_edma2_irq_init()
205 0, "eDMA2-ERR", fsl_edma); in fsl_edma2_irq_init()
209 fsl_edma->chans[i].chan_name, in fsl_edma2_irq_init()
210 fsl_edma); in fsl_edma2_irq_init()
219 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) in fsl_edma_irq_exit() argument
221 if (fsl_edma->txirq == fsl_edma->errirq) { in fsl_edma_irq_exit()
222 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); in fsl_edma_irq_exit()
224 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); in fsl_edma_irq_exit()
225 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); in fsl_edma_irq_exit()
229 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks) in fsl_disable_clocks() argument
234 clk_disable_unprepare(fsl_edma->muxclk[i]); in fsl_disable_clocks()
270 struct fsl_edma_engine *fsl_edma; in fsl_edma_probe() local
291 len = sizeof(*fsl_edma) + sizeof(*fsl_chan) * chans; in fsl_edma_probe()
292 fsl_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); in fsl_edma_probe()
293 if (!fsl_edma) in fsl_edma_probe()
296 fsl_edma->drvdata = drvdata; in fsl_edma_probe()
297 fsl_edma->n_chans = chans; in fsl_edma_probe()
298 mutex_init(&fsl_edma->fsl_edma_mutex); in fsl_edma_probe()
301 fsl_edma->membase = devm_ioremap_resource(&pdev->dev, res); in fsl_edma_probe()
302 if (IS_ERR(fsl_edma->membase)) in fsl_edma_probe()
303 return PTR_ERR(fsl_edma->membase); in fsl_edma_probe()
305 fsl_edma_setup_regs(fsl_edma); in fsl_edma_probe()
306 regs = &fsl_edma->regs; in fsl_edma_probe()
309 fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma"); in fsl_edma_probe()
310 if (IS_ERR(fsl_edma->dmaclk)) { in fsl_edma_probe()
312 return PTR_ERR(fsl_edma->dmaclk); in fsl_edma_probe()
315 ret = clk_prepare_enable(fsl_edma->dmaclk); in fsl_edma_probe()
322 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { in fsl_edma_probe()
326 fsl_edma->muxbase[i] = devm_ioremap_resource(&pdev->dev, res); in fsl_edma_probe()
327 if (IS_ERR(fsl_edma->muxbase[i])) { in fsl_edma_probe()
329 fsl_disable_clocks(fsl_edma, i); in fsl_edma_probe()
330 return PTR_ERR(fsl_edma->muxbase[i]); in fsl_edma_probe()
334 fsl_edma->muxclk[i] = devm_clk_get(&pdev->dev, clkname); in fsl_edma_probe()
335 if (IS_ERR(fsl_edma->muxclk[i])) { in fsl_edma_probe()
338 fsl_disable_clocks(fsl_edma, i); in fsl_edma_probe()
339 return PTR_ERR(fsl_edma->muxclk[i]); in fsl_edma_probe()
342 ret = clk_prepare_enable(fsl_edma->muxclk[i]); in fsl_edma_probe()
345 fsl_disable_clocks(fsl_edma, i); in fsl_edma_probe()
349 fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); in fsl_edma_probe()
351 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); in fsl_edma_probe()
352 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_probe()
353 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; in fsl_edma_probe()
355 fsl_chan->edma = fsl_edma; in fsl_edma_probe()
361 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); in fsl_edma_probe()
363 edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr); in fsl_edma_probe()
367 edma_writel(fsl_edma, ~0, regs->intl); in fsl_edma_probe()
368 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); in fsl_edma_probe()
372 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
373 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
374 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
376 fsl_edma->dma_dev.dev = &pdev->dev; in fsl_edma_probe()
377 fsl_edma->dma_dev.device_alloc_chan_resources in fsl_edma_probe()
379 fsl_edma->dma_dev.device_free_chan_resources in fsl_edma_probe()
381 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status; in fsl_edma_probe()
382 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; in fsl_edma_probe()
383 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; in fsl_edma_probe()
384 fsl_edma->dma_dev.device_config = fsl_edma_slave_config; in fsl_edma_probe()
385 fsl_edma->dma_dev.device_pause = fsl_edma_pause; in fsl_edma_probe()
386 fsl_edma->dma_dev.device_resume = fsl_edma_resume; in fsl_edma_probe()
387 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; in fsl_edma_probe()
388 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize; in fsl_edma_probe()
389 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; in fsl_edma_probe()
391 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; in fsl_edma_probe()
392 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; in fsl_edma_probe()
393 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in fsl_edma_probe()
395 platform_set_drvdata(pdev, fsl_edma); in fsl_edma_probe()
397 ret = dma_async_device_register(&fsl_edma->dma_dev); in fsl_edma_probe()
401 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); in fsl_edma_probe()
405 ret = of_dma_controller_register(np, fsl_edma_xlate, fsl_edma); in fsl_edma_probe()
409 dma_async_device_unregister(&fsl_edma->dma_dev); in fsl_edma_probe()
410 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); in fsl_edma_probe()
415 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); in fsl_edma_probe()
423 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev); in fsl_edma_remove() local
425 fsl_edma_irq_exit(pdev, fsl_edma); in fsl_edma_remove()
426 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); in fsl_edma_remove()
428 dma_async_device_unregister(&fsl_edma->dma_dev); in fsl_edma_remove()
429 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); in fsl_edma_remove()
436 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); in fsl_edma_suspend_late() local
441 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_suspend_late()
442 fsl_chan = &fsl_edma->chans[i]; in fsl_edma_suspend_late()
460 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); in fsl_edma_resume_early() local
462 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_resume_early()
465 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_resume_early()
466 fsl_chan = &fsl_edma->chans[i]; in fsl_edma_resume_early()
468 edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr); in fsl_edma_resume_early()
473 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); in fsl_edma_resume_early()