23 #define PX30_PMUGRF_OS_REG2		0x208
24 #define PX30_PMUGRF_OS_REG3		0x20c
26 #define RK3588_PMUGRF_OS_REG(n)		(0x200 + (n) * 4)
28 #define RK3128_GRF_SOC_CON0		0x140
29 #define RK3128_GRF_OS_REG1		0x1cc
30 #define RK3128_GRF_DFI_WRNUM		0x220
31 #define RK3128_GRF_DFI_RDNUM		0x224
32 #define RK3128_GRF_DFI_TIMERVAL		0x22c
34 #define RK3128_DDR_MONITOR_DISB		((1 << (16 + 6)) + (0 << 6))
36 #define RK3288_PMU_SYS_REG2		0x9c
37 #define RK3288_GRF_SOC_CON4		0x254
38 #define RK3288_GRF_SOC_STATUS(n)	(0x280 + (n) * 4)
39 #define RK3288_DFI_EN			(0x30003 << 14)
40 #define RK3288_DFI_DIS			(0x30000 << 14)
41 #define RK3288_LPDDR_SEL		(0x10001 << 13)
42 #define RK3288_DDR3_SEL			(0x10000 << 13)
44 #define RK3328_GRF_OS_REG2		0x5d0
46 #define RK3368_GRF_DDRC0_CON0		0x600
47 #define RK3368_GRF_SOC_STATUS5		0x494
48 #define RK3368_GRF_SOC_STATUS6		0x498
49 #define RK3368_GRF_SOC_STATUS8		0x4a0
50 #define RK3368_GRF_SOC_STATUS9		0x4a4
51 #define RK3368_GRF_SOC_STATUS10		0x4a8
52 #define RK3368_DFI_EN			(0x30003 << 5)
53 #define RK3368_DFI_DIS			(0x30000 << 5)
55 #define RK3528_PMUGRF_OFFSET		0x70000
56 #define RK3528_PMUGRF_OS_REG18		0x248
57 #define RK3528_PMUGRF_OS_REG19		0x24c
60 #define READ_DRAMTYPE_INFO(n)		(((n) >> 13) & 0x7)
61 #define READ_CH_INFO(n)			(((n) >> 28) & 0x3)
62 #define READ_DRAMTYPE_INFO_V3(n, m)	((((n) >> 13) & 0x7) | ((((m) >> 12) & 0x3) << 3))
63 #define READ_SYSREG_VERSION(m)		(((m) >> 28) & 0xf)
64 #define READ_LP5_BANK_MODE(m)		(((m) >> 1) & 0x3)
65 #define READ_LP5_CKR(m)			(((m) >> 0) & 0x1)
67 #define DDRMON_CTRL			0x04
68 #define CLR_DDRMON_CTRL			(0xffff0000 << 0)
69 #define LPDDR5_BANK_MODE(m)		((0x30000 | ((m) & 0x3)) << 7)
70 #define LPDDR5_EN			(0x10001 << 6)
71 #define DDR4_EN				(0x10001 << 5)
72 #define LPDDR4_EN			(0x10001 << 4)
73 #define HARDWARE_EN			(0x10001 << 3)
74 #define LPDDR2_3_EN			(0x10001 << 2)
75 #define SOFTWARE_EN			(0x10001 << 1)
76 #define SOFTWARE_DIS			(0x10000 << 1)
77 #define TIME_CNT_EN			(0x10001 << 0)
79 #define DDRMON_CH0_COUNT_NUM		0x28
80 #define DDRMON_CH0_DFI_ACCESS_NUM	0x2c
81 #define DDRMON_CH1_COUNT_NUM		0x3c
82 #define DDRMON_CH1_DFI_ACCESS_NUM	0x40
85 #define PMUGRF_OS_REG2			0x308
88 	DDR4 = 0,
96 	UNUSED = 0xFF
123 	/* 0: BG mode, 1: 16 Bank mode, 2: 8 bank mode */
125 	/* 0: clk:dqs = 1:2, 1: 1:4 */
128 	 * available mask, 1: available, 0: not available
156 	return 0;  in rk3128_dfi_disable()
163 	return 0;  in rk3128_dfi_enable()
168 	return 0;  in rk3128_dfi_set_event()
193 	return 0;  in rk3128_dfi_get_event()
221 	return 0;  in rk3288_dfi_disable()
228 	return 0;  in rk3288_dfi_enable()
233 	return 0;  in rk3288_dfi_set_event()
239 	u32 tmp, max = 0;  in rk3288_dfi_get_busier_ch()
240 	u32 i, busier_ch = 0;  in rk3288_dfi_get_busier_ch()
246 	for (i = 0; i < MAX_DMC_NUM_CH; i++) {  in rk3288_dfi_get_busier_ch()
282 	return 0;  in rk3288_dfi_get_event()
310 	return 0;  in rk3368_dfi_disable()
317 	return 0;  in rk3368_dfi_enable()
322 	return 0;  in rk3368_dfi_set_event()
349 	return 0;  in rk3368_dfi_get_event()
363 	u32 mon_idx = 0, val_6 = 0;  in rockchip_dfi_start_hardware_counter()
377 	for (i = 0; i < MAX_DMC_NUM_CH; i++) {  in rockchip_dfi_start_hardware_counter()
403 	u32 mon_idx = 0, i;  in rockchip_dfi_stop_hardware_counter()
408 	for (i = 0; i < MAX_DMC_NUM_CH; i++) {  in rockchip_dfi_stop_hardware_counter()
418 	u32 tmp, max = 0;  in rockchip_dfi_get_busier_ch()
419 	u32 i, busier_ch = 0;  in rockchip_dfi_get_busier_ch()
421 	u32 mon_idx = 0x20, count_rate = 1;  in rockchip_dfi_get_busier_ch()
431 	for (i = 0; i < MAX_DMC_NUM_CH; i++) {  in rockchip_dfi_get_busier_ch()
468 	return 0;  in rockchip_dfi_disable()
486 	return 0;  in rockchip_dfi_enable()
491 	return 0;  in rockchip_dfi_set_event()
508 	return 0;  in rockchip_dfi_get_event()
526 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in rk3588_dfi_init()
538 	if (READ_SYSREG_VERSION(val_3) >= 0x3)  in rk3588_dfi_init()
543 	data->mon_idx = 0x4000;  in rk3588_dfi_init()
554 	return 0;  in rk3588_dfi_init()
565 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in px30_dfi_init()
570 	node = of_parse_phandle(np, "rockchip,pmugrf", 0);  in px30_dfi_init()
579 	if (READ_SYSREG_VERSION(val_3) >= 0x3)  in px30_dfi_init()
588 	return 0;  in px30_dfi_init()
597 	node = of_parse_phandle(np, "rockchip,grf", 0);  in rk3128_dfi_init()
606 	return 0;  in rk3128_dfi_init()
616 	node = of_parse_phandle(np, "rockchip,pmu", 0);  in rk3288_dfi_init()
623 	node = of_parse_phandle(np, "rockchip,grf", 0);  in rk3288_dfi_init()
643 	return 0;  in rk3288_dfi_init()
661 	return 0;  in rk3368_dfi_init()
672 	data->regs = devm_platform_ioremap_resource(pdev, 0);  in rockchip_dfi_init()
683 	node = of_parse_phandle(np, "rockchip,pmu", 0);  in rockchip_dfi_init()
697 	return 0;  in rockchip_dfi_init()
708 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in rk3328_dfi_init()
713 	node = of_parse_phandle(np, "rockchip,grf", 0);  in rk3328_dfi_init()
727 	return 0;  in rk3328_dfi_init()
738 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in rk3528_dfi_init()
743 	node = of_parse_phandle(np, "rockchip,grf", 0);  in rk3528_dfi_init()
752 	if (READ_SYSREG_VERSION(val_19) >= 0x3)  in rk3528_dfi_init()
762 	return 0;  in rk3528_dfi_init()
830 			return 0;  in rockchip_dfi_probe()
833 		return 0;  in rockchip_dfi_probe()
849 	return 0;  in rockchip_dfi_probe()