Lines Matching refs:halg

3770 		      .halg.digestsize = MD5_DIGEST_SIZE,
3771 .halg.base = {
3791 .halg.digestsize = MD5_DIGEST_SIZE,
3792 .halg.base = {
3809 .halg.digestsize = SHA1_DIGEST_SIZE,
3810 .halg.base = {
3827 .halg.digestsize = SHA1_DIGEST_SIZE,
3828 .halg.base = {
3845 .halg.digestsize = SHA224_DIGEST_SIZE,
3846 .halg.base = {
3863 .halg.digestsize = SHA224_DIGEST_SIZE,
3864 .halg.base = {
3881 .halg.digestsize = SHA256_DIGEST_SIZE,
3882 .halg.base = {
3899 .halg.digestsize = SHA256_DIGEST_SIZE,
3900 .halg.base = {
3918 .halg.digestsize = SHA384_DIGEST_SIZE,
3919 .halg.base = {
3937 .halg.digestsize = SHA384_DIGEST_SIZE,
3938 .halg.base = {
3956 .halg.digestsize = SHA512_DIGEST_SIZE,
3957 .halg.base = {
3975 .halg.digestsize = SHA512_DIGEST_SIZE,
3976 .halg.base = {
3994 .halg.digestsize = SHA3_224_DIGEST_SIZE,
3995 .halg.base = {
4013 .halg.digestsize = SHA3_224_DIGEST_SIZE,
4014 .halg.base = {
4032 .halg.digestsize = SHA3_256_DIGEST_SIZE,
4033 .halg.base = {
4051 .halg.digestsize = SHA3_256_DIGEST_SIZE,
4052 .halg.base = {
4070 .halg.digestsize = SHA3_384_DIGEST_SIZE,
4071 .halg.base = {
4089 .halg.digestsize = SHA3_384_DIGEST_SIZE,
4090 .halg.base = {
4108 .halg.digestsize = SHA3_512_DIGEST_SIZE,
4109 .halg.base = {
4127 .halg.digestsize = SHA3_512_DIGEST_SIZE,
4128 .halg.base = {
4146 .halg.digestsize = AES_BLOCK_SIZE,
4147 .halg.base = {
4165 .halg.digestsize = AES_BLOCK_SIZE,
4166 .halg.base = {
4502 hash->halg.base.cra_module = THIS_MODULE; in spu_register_ahash()
4503 hash->halg.base.cra_priority = hash_pri; in spu_register_ahash()
4504 hash->halg.base.cra_alignmask = 0; in spu_register_ahash()
4505 hash->halg.base.cra_ctxsize = sizeof(struct iproc_ctx_s); in spu_register_ahash()
4506 hash->halg.base.cra_init = ahash_cra_init; in spu_register_ahash()
4507 hash->halg.base.cra_exit = generic_cra_exit; in spu_register_ahash()
4508 hash->halg.base.cra_flags = CRYPTO_ALG_ASYNC | in spu_register_ahash()
4510 hash->halg.statesize = sizeof(struct spu_hash_export_s); in spu_register_ahash()
4539 hash->halg.base.cra_driver_name); in spu_register_ahash()
4772 cdn = driver_algs[i].alg.hash.halg.base.cra_driver_name; in bcm_spu_remove()