47 static u32 pmbase;  variable
71 	pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase);  in speedstep_find_register()
72 	if (!(pmbase & 0x01)) {  in speedstep_find_register()
77 	pmbase &= 0xFFFFFFFE;  in speedstep_find_register()
78 	if (!pmbase) {  in speedstep_find_register()
83 	pr_debug("pmbase is 0x%x\n", pmbase);  in speedstep_find_register()
107 	value = inb(pmbase + 0x50);  in speedstep_set_state()
109 	pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);  in speedstep_set_state()
115 	pr_debug("writing 0x%x to pmbase 0x%x + 0x50\n", value, pmbase);  in speedstep_set_state()
118 	pm2_blk = inb(pmbase + 0x20);  in speedstep_set_state()
120 	outb(pm2_blk, (pmbase + 0x20));  in speedstep_set_state()
123 	outb(value, (pmbase + 0x50));  in speedstep_set_state()
127 	outb(pm2_blk, (pmbase + 0x20));  in speedstep_set_state()
130 	value = inb(pmbase + 0x50);  in speedstep_set_state()
135 	pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);  in speedstep_set_state()