60 	int ret = 0;  in px30_get_soc_info()
61 	u8 value = 0;  in px30_get_soc_info()
64 		return 0;  in px30_get_soc_info()
67 				     "performance") >= 0) {  in px30_get_soc_info()
75 	if (*bin >= 0)  in px30_get_soc_info()
84 	int ret = 0;  in rk3288_get_soc_info()
85 	u8 value = 0;  in rk3288_get_soc_info()
90 	if (of_property_match_string(np, "nvmem-cell-names", "special") >= 0) {  in rk3288_get_soc_info()
96 		if (value == 0xc)  in rk3288_get_soc_info()
97 			*bin = 0;  in rk3288_get_soc_info()
107 	if (of_property_match_string(np, "nvmem-cell-names", name) >= 0) {  in rk3288_get_soc_info()
113 		if (value & 0x2)  in rk3288_get_soc_info()
115 		else if (value & 0x01)  in rk3288_get_soc_info()
118 	if (*bin >= 0)  in rk3288_get_soc_info()
125 				     "process") >= 0) {  in rk3288_get_soc_info()
131 		if (soc_is_rk3288() && (value == 0 || value == 1))  in rk3288_get_soc_info()
132 			*process = 0;  in rk3288_get_soc_info()
134 	if (*process >= 0)  in rk3288_get_soc_info()
144 	int ret = 0;  in rk3399_get_soc_info()
145 	u8 value = 0;  in rk3399_get_soc_info()
148 		return 0;  in rk3399_get_soc_info()
151 				     "specification_serial_number") >= 0) {  in rk3399_get_soc_info()
161 		if (value == 0xb) {  in rk3399_get_soc_info()
162 			*bin = 0;  in rk3399_get_soc_info()
163 		} else if (value == 0x1) {  in rk3399_get_soc_info()
165 						     "customer_demand") >= 0) {  in rk3399_get_soc_info()
173 				if (value == 0x0)  in rk3399_get_soc_info()
174 					*bin = 0;  in rk3399_get_soc_info()
178 		} else if (value == 0x10) {  in rk3399_get_soc_info()
184 	if (*bin >= 0)  in rk3399_get_soc_info()
193 	int ret = 0;  in rk3588_get_soc_info()
194 	u8 value = 0;  in rk3588_get_soc_info()
197 		return 0;  in rk3588_get_soc_info()
200 				     "specification_serial_number") >= 0) {  in rk3588_get_soc_info()
210 		if (value == 0xd)  in rk3588_get_soc_info()
213 		else if (value == 0xa)  in rk3588_get_soc_info()
216 	if (*bin < 0)  in rk3588_get_soc_info()
217 		*bin = 0;  in rk3588_get_soc_info()
229 	u32 opp_flag = 0;  in rk3588_change_length()
230 	int ret = 0;  in rk3588_change_length()
266 		return 0;  in rk3588_set_supported_hw()
269 	supported_hw[0] = BIT(bin);  in rk3588_set_supported_hw()
278 	return 0;  in rk3588_set_supported_hw()
284 	if (volt_sel < 0)  in rk3588_set_soc_info()
285 		return 0;  in rk3588_set_soc_info()
286 	if (bin < 0)  in rk3588_set_soc_info()
287 		bin = 0;  in rk3588_set_soc_info()
292 	return 0;  in rk3588_set_soc_info()
300 		return 0;  in rk3588_cpu_set_read_margin()
302 		return 0;  in rk3588_cpu_set_read_margin()
306 		regmap_write(opp_info->grf, 0x20, 0x001c0000 | (rm << 2));  in rk3588_cpu_set_read_margin()
307 		regmap_write(opp_info->grf, 0x28, 0x003c0000 | (rm << 2));  in rk3588_cpu_set_read_margin()
308 		regmap_write(opp_info->grf, 0x2c, 0x003c0000 | (rm << 2));  in rk3588_cpu_set_read_margin()
309 		regmap_write(opp_info->grf, 0x30, 0x00200020);  in rk3588_cpu_set_read_margin()
311 		regmap_write(opp_info->grf, 0x30, 0x00200000);  in rk3588_cpu_set_read_margin()
314 		regmap_write(opp_info->dsu_grf, 0x20, 0x001c0000 | (rm << 2));  in rk3588_cpu_set_read_margin()
315 		regmap_write(opp_info->dsu_grf, 0x28, 0x003c0000 | (rm << 2));  in rk3588_cpu_set_read_margin()
316 		regmap_write(opp_info->dsu_grf, 0x2c, 0x003c0000 | (rm << 2));  in rk3588_cpu_set_read_margin()
317 		regmap_write(opp_info->dsu_grf, 0x30, 0x001c0000 | (rm << 2));  in rk3588_cpu_set_read_margin()
318 		regmap_write(opp_info->dsu_grf, 0x38, 0x001c0000 | (rm << 2));  in rk3588_cpu_set_read_margin()
319 		regmap_write(opp_info->dsu_grf, 0x18, 0x40004000);  in rk3588_cpu_set_read_margin()
321 		regmap_write(opp_info->dsu_grf, 0x18, 0x40000000);  in rk3588_cpu_set_read_margin()
326 	return 0;  in rk3588_cpu_set_read_margin()
332 	int ret = 0;  in rv1126_get_soc_info()
333 	u8 value = 0;  in rv1126_get_soc_info()
335 	if (of_property_match_string(np, "nvmem-cell-names", "performance") >= 0) {  in rv1126_get_soc_info()
341 		if (value == 0x1)  in rv1126_get_soc_info()
344 			*bin = 0;  in rv1126_get_soc_info()
346 	if (*bin >= 0)  in rv1126_get_soc_info()
444 	struct dev_pm_opp_supply *old_supply_vdd = &data->old_opp.supplies[0];  in cpu_opp_helper()
446 	struct dev_pm_opp_supply *new_supply_vdd = &data->new_opp.supplies[0];  in cpu_opp_helper()
448 	struct regulator *vdd_reg = data->regulators[0];  in cpu_opp_helper()
457 	int ret = 0;  in cpu_opp_helper()
524 	return 0;  in cpu_opp_helper()
554 	int ret = 0;  in rockchip_cpufreq_cluster_init()
555 	u32 freq = 0;  in rockchip_cpufreq_cluster_init()
570 	np = of_parse_phandle(dev->of_node, "operating-points-v2", 0);  in rockchip_cpufreq_cluster_init()
635 	return 0;  in rockchip_cpufreq_cluster_init()
660 	return 0;  in rockchip_cpufreq_adjust_power_scale()
669 	int ret = 0;  in rockchip_cpufreq_opp_set_rate()
696 	int ret = 0;  in rockchip_cpufreq_suspend()
732 	return 0;  in rockchip_cpufreq_add_monitor()
743 	return 0;  in rockchip_cpufreq_remove_monitor()
751 		return 0;  in rockchip_cpufreq_remove_dsu_qos()
760 	return 0;  in rockchip_cpufreq_remove_dsu_qos()
771 		return 0;  in rockchip_cpufreq_add_dsu_qos_req()
780 		if (ret < 0) {  in rockchip_cpufreq_add_dsu_qos_req()
786 	return 0;  in rockchip_cpufreq_add_dsu_qos_req()
832 		if (idle_disable_refcnt == 0)  in rockchip_cpufreq_idle_state_disable()
833 			cpu_latency_qos_update_request(&idle_pm_qos, 0);  in rockchip_cpufreq_idle_state_disable()
836 		if (--idle_disable_refcnt == 0)  in rockchip_cpufreq_idle_state_disable()
843 	return 0;  in rockchip_cpufreq_idle_state_disable()
871 	return 0;  in rockchip_cpufreq_idle_state_disable()
885 		return 0;  in rockchip_cpufreq_update_dsu_req()
946 	return 0;  in rockchip_cpufreq_panic_notifier()
956 	struct cpufreq_dt_platform_data pdata = {0};  in rockchip_cpufreq_driver_init()